Title:
半導体装置
Document Type and Number:
Japanese Patent JP7256246
Kind Code:
B2
Abstract:
An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.
Inventors:
Sanpei Yamazaki
Jun Oyama
Kiyoshi Kato
Jun Oyama
Kiyoshi Kato
Application Number:
JP2021184061A
Publication Date:
April 11, 2023
Filing Date:
November 11, 2021
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H10B12/00; G11C11/405; G11C11/408; G11C11/4091; G11C11/56; H01L29/786
Domestic Patent References:
| JP2009094495A | ||||
| JP2009016844A | ||||
| JP2006294116A | ||||
| JP62274773A |
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