Title:
半導体装置
Document Type and Number:
Japanese Patent JP7397944
Kind Code:
B2
Abstract:
An adder circuit inhibiting overflow is provided. A first memory, a second memory, a third memory, and a fourth memory are included. A step of supplying first data with a sign to the first memory and supplying the first data with a positive sign stored in the first memory, to the second memory; a step of supplying the first data with a negative sign stored in the second memory, to the third memory; a step of generating second data by adding the first data with a positive sign stored in the second memory and the first data with a negative sign stored in the third memory; and a step of storing the second data in the fourth memory are included. When the second data stored in the fourth memory are all second data with a positive sign or all second data with a negative sign, all the second data stored in the fourth memory are added.
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Inventors:
Shunpei Yamazaki
Hajime Kimura
Takahiro Fukudome
Hajime Kimura
Takahiro Fukudome
Application Number:
JP2022167346A
Publication Date:
December 13, 2023
Filing Date:
October 19, 2022
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G06F7/499; G06G7/60; H01L21/8234; H01L27/06; H01L27/088; H01L29/786; H10B12/00; H10B41/70
Domestic Patent References:
| JP2003241958A | ||||
| JP2006277019A | ||||
| JP2002111447A |
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