Title:
BUS INTERFACE DEVICE, RELAY DEVICE, AND BUS SYSTEM COMPRISING BOTH
Document Type and Number:
WIPO Patent Application WO/2014/115207
Kind Code:
A1
Abstract:
An integrated circuit bus system comprising networked semiconductor buses, which improves the usage efficiency of buffers provided in relay devices. In the bus system, a plurality of bus interface devices and relay devices are connected by packet switching buses constructed on an integrated circuit. The bus interface devices are connected to a plurality of transmission nodes which have different numbers of bits of data to be transmitted in one operation cycle of the bus system. The bus interface devices transmit packets generated from: data received from the connected transmission nodes; and header information including size information that indicates the numbers of bits pertaining to the connected transmission nodes. The relay devices analyse the packets, acquire the size information from the header information, set the storage amount in a buffer on the basis of the acquired size information, and store the received packets in the buffer.
Inventors:
YOSHIDA ATSUSHI
TOKUTSU SATORU
ISHII TOMOKI
YAMAGUCHI TAKAO
SOGA YUUKI
TOKUTSU SATORU
ISHII TOMOKI
YAMAGUCHI TAKAO
SOGA YUUKI
Application Number:
PCT/JP2013/006823
Publication Date:
July 31, 2014
Filing Date:
November 20, 2013
Export Citation:
Assignee:
PANASONIC CORP (JP)
International Classes:
H04L13/08; H04L45/74
Foreign References:
| JP2006135379A | 2006-05-25 |
Other References:
ANDREAS GERSTLAUER: "Automatic Layer-Based Generation of System-On-Chip Bus Communicatior Models, Computer-Aided Design of Integrated Circuits and Systems", IEEE TRANSACTIONS ON, vol. 26, no. ISSUE:, September 2007 (2007-09-01)
Attorney, Agent or Firm:
OKUDA, SEIJI (JP)
Seiji Okuda (JP)
Seiji Okuda (JP)
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