Title:
CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2011/142066
Kind Code:
A1
Abstract:
Disclosed is a method for the simulation of a circuit which includes: a transistor of which the source region and the drain region are formed of a material (such as SiGe) and with a lattice constant that are different from those of the semiconductor substrate; and a peripheral active region formed in the periphery of the transistor, wherein the active region has a gate electrode formed thereon, and the regions of the peripheral active region on which the gate electrode is not formed are made of SiGe or the like. In the disclosed circuit simulation method, the electric characteristics of the transistor (14) (such as the current passing therethrough and the threshold voltage) are calculated on the basis of the gate length (L) of the gate electrode (13) and the channel width (W) of the transistor (14), and the distance (19) between the one of the two ends of the peripheral active region (12) on the side of the transistor (14) and the gate electrode (15) formed on the active region (12). Thus, the electric characteristics of the transistor (14) can be simulated with high accuracy.
Inventors:
ISHIZU TOMOYUKI
Application Number:
PCT/JP2011/001046
Publication Date:
November 17, 2011
Filing Date:
February 24, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
ISHIZU TOMOYUKI
ISHIZU TOMOYUKI
International Classes:
G06F17/50; H01L21/336; H01L21/82; H01L21/8234; H01L27/088; H01L29/78
Foreign References:
| JP2008085030A | 2008-04-10 | |||
| JP2009025891A | 2009-02-05 | |||
| JP2006178907A | 2006-07-06 | |||
| JP2009087169A | 2009-04-23 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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Claims:
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