A/D CONVERSION INTEGRATED CIRCUIT - UNIV SHIZUOKA NAT UNIV CORP

Title:

A/D CONVERSION INTEGRATED CIRCUIT

Document Type and Number:

WIPO Patent Application WO/2010/137660

Kind Code:

A1

Abstract:

Disclosed is an A/D conversion integrated circuit which includes a plurality of A/D converters capable of reducing the propagation of noise caused by capacitive coupling from conductors transmitting digital signals. At each A/D converter (13), an input (15) receives an analog signal (SA) to be converted from analog to digital. An output (17) provides at least part of a digital signal (SD) of a predetermined number of bits representing the analog signal (SA). A sub A/D conversion circuit (19) receives the analog signal (SA) and generates a signal (SDP) representing one or a plurality of bit values among the digital signal (SD), and provides the signal (SDP) to the output (17). An input (21a) of a control circuit (21) is connected to an output (19a) of the sub A/D conversion circuit (19), and provides the control signal (SCONT) corresponding to the signal (SDP). The control signal (SCONT) comprises a waveform including the transition from the voltage level L1 to the voltage level L2, and the transition from the voltage level L2 to the voltage level L1.

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Inventors:

KAWAHITO SHOJI (JP)

Application Number:

PCT/JP2010/059022

Publication Date:

December 02, 2010

Filing Date:

May 27, 2010

Export Citation:

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Assignee:

UNIV SHIZUOKA NAT UNIV CORP (JP)
KAWAHITO SHOJI (JP)

International Classes:

H03M1/40; H03M1/08

Foreign References:

EP2056461A1	2009-05-06
JP2004135321A	2004-04-30
JP2008092134A	2008-04-17
JP2004128637A	2004-04-22

Other References: