DC level-shifting in an analog-to-digital converter (ADC) semiconductor device is traditionally performed with a CMOS source-follower circuit. An example of such a circuit is shown in FIG. 2 (prior art). The DC level-shifting provided is desired to be highly linear to avoid introduction of error into the output voltage. In other words, it is desirable that a constant voltage shift be added by the DC level-shifting circuit across the full input voltage range. Two main sources of nonlinearity in traditional CMOS source-follower circuits are variations with input voltage of the drain-source current (IDS) and the drain-source voltage (VDS) of the MOS transistor (mop,) in the CMOS source-follower circuit.

One prior technique to improve the linearity of a traditional CMOS source-follower circuit attempted to reduce the variation of IDS with input voltage. This prior technique connected a constant current source to the drain terminal of the MOS transistor (mop1) and added a second MOS transistor (MN i) to handle additional current flow. FIG. 3 (prior art) shows an example of such a circuit. This prior technique, however, did not address variations in VDS suffered by traditional CMOS source-follower level-shifting circuits.

The object of the present invention is to provide a DC level-shifting circuit that reduces both IDS and VDS variations to achieve a highly linear response.

SUMMARY OF THE INVENTION The present invention provides a unique and advantageous highly linear source-follower DC level-shifting circuit. In particular, the circuit contemplated by the present invention is a modification to a traditional CMOS source-follower DC level-shifting circuit that greatly improves the linearity of the traditional device. This modification adds a second CMOS source-follower circuit that reduces both variations of the drain-source current (its) and variations in the drain-source voltage (VDS) of the MOS transistor in the traditional CMOS source-follower DC level-shifting circuit.

In general respects, the present invention is an instrumentation-amplifier DC level- shifting circuit for an analog-to-digital converter that includes a source-follower DC level- shifting circuit, and a second source-follower circuit connected to the first source-follower to enhance the linear response of the circuit. This circuit may include a first MOS transistor, a first current source connected to a source terminal of the first MOS transistor, a second current source or some other non-zero impedance device connected to a drain terminal of the first MOS transistor, and a DC linear-response enhancing circuit connected between the source terminal and the drain terminal of the first MOS transistor. The DC linear-response enhancing circuit may include a near-unity gain buffer plus a level shifter, which in turn may be a second source-follower circuit including a second MOS transistor. The circuit according to the present invention may be implemented as an NMOS version or a PMOS version, and the current source implementations may also be either NMOS or PMOS implementations.

In other broad respects, the present invention is a highly linear DC level-shifting source-follower circuit for an instrumentation amplifier in an analog-to-digital converter having a first source-follower circuit, including a first MOS transistor having a source terminal and a drain terminal defining a voltage drop VDS, and a VDS voltage-fixing circuit connected to the first source-follower circuit. The VDS voltage-fixing circuit may be a second source-follower circuit including a second MOS transistor. As above, the present invention may be

implemented as an NMOS version or PMOS version. The circuit of the present invention may further include a first current source connected to the source terminal of the first MOS transistor, and a second current source connected to the drain terminal of the first MOS transistor.

In further general respects, the present invention is a highly linear DC level-shifting circuit having a first source-follower circuit including a first MOS transistor having a drain terminal, a gate terminal providing a circuit input and a source terminal providing a circuit output; and a second source-follower circuit including a second MOS transistor having a gate terminal connected to the source terminal of first MOS transistor, and a source terminal connected to the drain terminal of the first MOS transistor. This circuit may also have a first current source connected to the drain terminal of the first MOS transistor, and a second current source connected to the a source terminal of the first MOS transistor.

DESCRIPTION OF THE DRAWINGS It is to be noted that the appended drawings illustrate only particular embodiments of the invention and are, therefore, not to be considered limiting of its scope, for the invention may admit to other effective embodiments.

FIG. 1A is a block diagram of a typical analog-to-digital converter.

FIG. 1B is a block diagram of an application for a DC level-shifting circuit in an instrumentation amplifier of an analog-to-digital converter.

FIG. 2 (prior art) is a circuit diagram for a traditional source-follower DC level-shifting circuit.

FIG. 3 (prior art) is a circuit diagram for a prior technique for modifying a traditional source-follower DC level-shifting circuit to reduce IDS variations.

FIG. 4 is a circuit diagram for a highly linear source-follower DC level-shifting circuit according to the present invention.

FIG. 5A is a circuit diagram for a PMOS version of a highly linear source-follower DC level-shifting circuit according to the present invention.

FIG. 5B is a circuit diagram for a PMOS version of a highly linear source-follower DC level-shifting circuit according to the present invention with a more detailed diagram for the current source implementations.

FIG. 6A is a circuit diagram for an NMOS version of a highly linear source-follower DC level-shifting circuit according to the present invention.

FIG. 6B is a circuit diagram for an NMOS version of a highly linear source-follower DC level-shifting circuit according to the present invention with a more detailed diagram for the current source implementations.

FIG. 7 is a graphical representation of a measure of linearity by comparing an ideal linear circuit response with an actual circuit response. (Nonlinearity of the actual circuit response is not drawn to scale.) FIG. 8 is a diagram of a HSPICE model simulation for comparing the linearity of a traditional source-follower DC level-shifting circuit (FIG. 2 (prior art)), and of a prior technique for modifying a source-follower DC level-shifting circuit (FIG. 3 (prior art)), with a source-follower DC level-shifting circuit according to the present invention.

DETAILED DESCRIPTION FIG. 1A shows a block diagram of a typical integrated circuit analog-to-digital converter 100 with traditional components. Analog-to-digital converter 100 includes an instrumentation amplifier 102, a programmable gain amplifier 104, a signal modulator 106, and a programmable digital filter 108. The signal modulator 106 may be a differential fourth order delta-sigma modulator. The references AIN+ and AlN- represent the analog inputs to the device. The references VREF+ and VREF represent the reference voltages applied to the signal modulator 106. Analog-to-digital converter semiconductor devices that include this general structure are available from Crystal Semiconductor Corporation, Austin, Texas. The present invention, however, relates to a level-shifting circuit for use in the instrumentation amplifier for an analog-to-digital converter semiconductor device.

FIG. 1B depicts an example of an application for a DC level-shifter for an instrumentation amplifier for an analog-to-digital converter semiconductor device. As shown in FIG. 1B, both a positive input voltage (Vj+) and a negative input voltage (Vj-) may be connected to level-shifting circuits. In the example depicted in FIG. 1B, the level-shifters 112 and 114 are designed to add a constant voltage (X) to the input voltages (Vj+ and Vj-). Thus, the output of the level-shifters (V+ and V-) are the input voltages (V + and V,-) plus a constant voltage (X).

An indication of the desirability of DC level-shifting may be gained from a brief analysis of an application of level-shifters with the two opamps 116 and 118 as shown in FIG.

1B. Each opamp 116 and 118 provide a gain (A) that is dependent upon the resistor connections (R1, R2). The output of the level-shifters 112 and 114 (V+ and V-) are connected to the positive inputs of the two opamps 116 and 118. The negative inputs of both opamps 116 and 118 are connected together through resistor R1. The negative input of the positive side opamp 116 is connected to the positive output voltage (V0+) through a resistor R2, and the negative terminal of the negative side opamp 118 is connected to the negative output voltage

(V0-) through another resistor R2. In this circuit, the input/output relationship of the opamps 116 and 118 is as follows: <BR> <BR> <BR> <BR> <BR> (V+)+(V-) (V+)-(V-)<BR> (V0+)= +A 2 2 (V+)+(V-) (V+)-(V-) (V0-)= -A <BR> <BR> 2 2<BR> A 2R2+R <BR> <BR> <BR> RI The desirability of level-shifters can be demonstrated by supposing that there are no level-shifters in the circuit in FIG. 1B. In such a situation, if X = 0, V+ = Vj+, and V- = Vj-. Assuming that A = 10, Vj+ = -100 mv, and Vj- = 0 volts, and using the above equations, V0+ = -550 mv and VO- = 450 mv. This result would require that the two opamps 116 and 118 be run from a negative power supply because one of the outputs is below ground.

If PMOS source-follower DC level-shifting circuits are added with a Vos having an absolute value of 1 volts (i.e., the constant X = 1 volt), this need for a negative supply is eliminated.

Using the above equations with DC level-shifting circuits in place, V+ = X + Vj+ = 900 mv, and V- = X + V- = 1000 mv. Again using the above equations, V0+ = 450 mv, and V0- = 1.45 volts. Although the differential output (V0+ - V0 ) is unchanged, the opamps 116 and 118 can now be run from a single positive supply. This is an advantage for an instrumentation amplifier for an analog-to-digital converter semiconductor device. Thus, in the design of the instrumentation amplifier portion of an analog-to-digital converter semiconductor device, it is desirable to include DC level-shifters. It is also advantageous for the DC level-shifters to have a linear input/output response across the voltage input range. In other words, it is desirable for the DC shift provided by the level-shifters to be constant for any given input voltage. This technique allows an ADC to accept and process inputs that go below ground without the need for a negative supply to be connected to the ADC.

The present invention provides a unique and advantageous DC level-shifting circuit that has a highly linear response. In particular, the circuit contemplated by the present invention is

a modification to a traditional CMOS source-follower DC level-shifting circuit that greatly improves linearity by reducing variations with input voltage of the drain-source current (IDS) and drain-source voltage (VDS) of the MOS transistor in the traditional CMOS source-follower DC level-shifting circuit.

An example of a traditional simple source-follower circuit is shown in FIG. 2 (prior art). In this circuit, the input voltage (VIN) is applied between ground (GND) and the gate of a MOS transistor. In FIG. 2 (prior art) the MOS transistor (MP1) is depicted as a p-channel MOS transistor. The drain terminal of Mp, is connected to ground (GND). A constant current source I is connected between the source terminal of Mpl and the supply voltage (VDD).

For this application, the body (or substrate) terminal of Mpl may be connected to the source terminal. This connection results in a p-n junction between the substrate and the channel of the MOS transistor, which has a constant reverse bias. Because of this p-n junction, the body (or substrate) does not play a role in circuit operation, and the existence of the body can essentially be ignored. This connection, therefore, tends to keep the body of the MOS transistor from acting as a second gate (known as the "body effect"), which may cause considerable degradation in circuit performance. The body of Mp1, however, may also be connected to supply voltage (VDD).

The voltage output (VOUT) of the simple source-follower DC level-shifting circuit in FIG. 2 (prior art) is taken between ground (GND) and the source terminal of Mop1. VOUT in turn drives the LOAD. The LOAD cell may consist of conductive (draws DC current) and reactive (draws AC current) parts. The voltage shift provided by this simple source-follower circuit is given by the following equation: VSHI=T = VOUT - VIN = VGs(MPl).

As VIN changes, the LOAD generally draws different amounts of current. The change in LOAD current causes a change in Ides, which, together with a change in VDS (Mp1), will cause a change in VGs (MP1) which is nonlinear with respect to VIN. In other words, the linearity of the simple source-follower circuit suffers due to changes in VG5 which are caused

by changes in VIN. This is an undesirable result for a level-shifting circuit used in an instrumentation amplifier for an analog-to-digital converter semiconductor device.

One prior technique for improving the linear response of a simple source-follower DC level-shifting circuit is shown in FIG. 3 (prior art). As seen in FIG. 3 (prior art), the simple source-follower circuit of FIG. 2 (prior art) is changed in two ways. First, a constant current source I2 has been connected between the drain terminal of MP1 and ground (GND). Second, an n-channel MOS transistor (MNI) has been connected such that the gate terminal of MN1 is connected to the drain terminal of MP1, the source terminal of MN1 is connected to ground (GND), and the drain terminal of MN1 is connected to the source terminal of MP1. This circuit attempts to reduce variations in V05 (MP1) by fixing IDS (MP1). IDS (MP1) is fixed by including a constant current source I2 and a complimentary MOS transistor (MN I). When VIN varies and the LOAD current in turn varies, the varying LOAD current is now supplied by the additional complementary MOS transistor Mini. This in turn reduces the resulting variation in V05 (Mp1), which increases the linearity of the simple source-follower amplifier. It is noted that because the first MOS transistor in FIG. 3 (prior art) is a p-channel MOS transistor, the complimentary MOS transistor is an n-channel MOS transistor.

Unlike this prior technique, the present invention improves linearity by reducing variations in VDS (Mp1), as well as variations in 1D5 (MP1), linearizing V05 with VIN. FIG. 4 represents a general diagram of a highly linear source-follower amplifier, according to the present invention, that may be used as a DC level-shifter for an instrumentation amplifier in an analog-to-digital converter semiconductor device. It may be assumed that 1DS (Mp1) is fixed in the FIG. 4 embodiment of the invention because the LOAD may be assumed to draw no DC current. FIG. 4 depicts the general circuit for a simple source-follower amplifier with the addition of a linear-response enhancing circuit 402 that is connected between the source and drain terminals of MOS transistor Mpl and that acts to fix VDS (MP1). As with the simple source-follower circuit shown in FIG. 2 (prior art), the input voltage (VIN) is connected between ground (GND) and the gate terminal of MOS transistor Mp1. An impedance (Z) is connected between the drain terminal of MOS transistor MP1 and ground (GND), and may be

any impedance other than a voltage source. A DC current source (IDS) is connected between the source terminal of MOS transistor Mp1 and the supply voltage (VDD). The output voltage (VO) is supplied between ground and the source terminal of MOS transistor Mp1. Because the LOAD in an analog-to-digital converter application is expected to be MOS transistor gates, it may be assumed that the LOAD in FIG. 4 is reactive only and will draw no DC current. The LOAD, therefore, is shown connected with a dotted line. The linear-response enhancing circuit 402 provides the unique and advantageous result of the present invention. Preferably, linear-response enhancing circuit 402 includes an ideal unity gain buffer (B), which has an infinite input impedance and zero output impedance, and includes a constant DC voltage drop VDROP.

The linear-response enhancing circuit improves the linear response of this DC level- shifter by reducing variations in both VDS and IDS of a simple source-follower circuit. By keeping VDS and IDS of the source-follower circuit (MP1) constant, VGS is very linear with VIN.

As will be shown in FIGS. SA, 5B, 6A and 6B in certain embodiments, the linear-response enhancing circuit 402 may be implemented using a second source-follower circuit connected to the first source-follower circuit. This resulting double source-follower circuit provides significant improvement in linearity when used as a DC level-shifting circuit in an analog-to- digital converter semiconductor device.

FIG. 5A depicts a circuit diagram for a PMOS version of a highly linear source- follower DC level-shifting circuit according to the present invention. In addition to fixing IDS (Mp1) as does the prior technique shown in FIG. 3 (prior art), the highly linear source-follower amplifier depicted in FIG. 5A also fixes VDS (MP1), thereby reducing the variation in VGS (Mp1) and increasing linearity of the level-shifter. In FIG. 5A, a simple source-follower Mp1 is followed by a second source-follower Mint. The input voltage (VIN) is connected between the gate terminal of Mp1 and ground (GND). A constant current source I1 is connected between the source terminal of Mp1 and the supply voltage (VDD). A second constant current source I2 is connected between the drain terminal of MP1 and ground (GND). The gate terminal of the second source-follower MNI is connected to the source terminal of MPI The source terminal of

MNI is connected to the drain terminal of MP1, and the drain terminal of MNI is connected to the supply voltage (VDD). It is also noted that the body terminal of MP1 is connected to the source terminal of MPI, while the body terminal of MNI is connected to ground (GND). The body terminal of MNI, however, may also be connected to the source terminal of MNI if the semiconductor manufacturing process allows. By adding the second source-follower circuit to a simple source-follower circuit, the linearity of the circuit as a DC level-shifter is greatly enhanced. The variation in VDS (Mp1) is reduced from nearly AVIN to #VGS (MN i). Also, the currents of both MPX and MN1 are substantially fixed and are represented by the following equations: IDS (Mp1) = Il; and IDS (MNI) = I2 - I1 FIG. 5B shows a more detailed circuit diagram of FIG. 5A, including a transistor implementation of the current sources II and I2 shown in FIG. 5A. In addition, the dimensions for the MOS transistor devices in one embodiment are shown in FIG. 5B. These measurements are given in width versus length ratios (W/L) for each MOS transistor shown in FIG. 5B. For example, MN1 may have a ratio of 4y/8y, and MP1 may have a ratio of 8y/4y.

This circuit provides a highly linear source-follower circuit that may be used as a DC level- shifter.

Looking to I1 in FIG. 5B, it is shown that I, may be implemented using four p-channel MOS transistors (MP12, MP14, MP16, MP18) connected together plus a bias current (IBIAS1). In particular, the source terminals for Mp,2 and Mp,6 may be connected to the supply voltage (VDD) and the gate terminals of Mp,2 and Mp,6 may be connected together. In addition, the gate terminal of Mp,2 may be connected to the drain terminal of MP12, Next, the source terminal of MP14, may be connected to the drain terminal of MP12, and the drain terminal of MP14 may be connected to the constant bias current IBIAS1 This bias current (IBIASI) may be 2 µA. The drain terminal of MP14 may also be connected to the gate terminal of MP14. In addition, the source terminal of Mp18 may be connected to the drain terminal of MP16, and the gate terminal of MP18 may be connected to the gate terminal of Mpj4. The drain terminal of MP18 is connected to the

source terminal of MP1, which is also the output voltage (VOUT). As shown in FIG. 5B, the ratios for MP12 and MP14 may be 4µ/2µ, and the ratios for MP16 and MP18 may be 2 x 4µ/2µ.

Looking to I2 in FIG. 5B, it is shown that I2 may be implemented using two n-channel MOS transistors (MNl2, MN14) connected together plus a bias current (IBIAS2). In particular, the source terminals of MN12 and MNI4 may be connected to ground (GND), and the gate terminals of MNI2 and MN14 may be connected together. In addition, the drain terminal of MNI2 may be connected to the drain terminal of MP1. Also, the drain terminal of MN14 may be connected to a bias current (1BIAs2), which may 2 µA. Finally, the gate terminal of MN14 may be connected to the drain terminal of MN14. It is also shown in FIG. 5B that the ratio for MN14 may be 4M/2M, and the ratio for MN12 may be 6 x 4µ/2µ.

As mentioned above, the present invention may also be implemented as an NMOS version, which is shown in FIGS. 6A and 6B. FIG 6A corresponds to FIG. 5A, and FIG. 6B corresponds to FIG. 5B. Thus, it is noted that MNI in FIG. 6A corresponds to Mp, in FIG.

5A, and Mp, in FIG. 6A corresponds to MNI in FIG. 5A.

As shown in FIG. 6A for the NMOS version, VlN is connected between ground (GND) and the gate terminal of MN1. A constant current source I is connected between the source terminal of MNI and ground (GND). Another current source I2 is connected between the supply voltage (VDD) and the drain terminal of MN1. A second source-follower defined by Mp, is connected to the first source-follower defined by MN1. The gate terminal of Mp, is connected to the source terminal of MN1. The source terminal of Mp, is connected to the drain terminal of MN1. And the drain terminal of Mp, is connected to ground (GND). In the embodiment shown in FIG. 6A, the body terminal of MNI is connected to the source terminal of MN1, as discussed above with respect to Mp, in FIG. 5A. The body terminal of Mp, is connected to the circuit supply voltage (VDD). The body terminal of Mp, may also be connected to the source terminal of Mp, if the manufacturing process allows. VOUT is taken between ground (GND) and the source terminal of MN1. Again, the LOAD is connected to VOUT by dotted lines to show that the LOAD is expected to provide no DC current path.

FIG. 6B provides a more detailed circuit diagram for the NMOS version shown in FIG.

6A, and includes a transistor implementation of current sources I, and 12. Similar to FIG. 5B, FIG. 6B also shows example width versus length (W/L) ratios for the MOS transistors. For example, the ratio for MNI may be 8µ/4µ, and the ratio for Mp, may be 4y/8y.

Looking to the box corresponding to I2, it is shown that I2 may be implemented using two p-channel MOS transistors (MP12, Mpl4) plus a bias current (IBIAS2). In particular, the source terminals of Mp,2 and Mp,4 may be connected to the supply voltage (VDD), and the gate terminals of Mp,2 and MP14 may be connected together. The gate terminal of Mp12 may also be connected to the drain terminal of MP12. The drain terminal of MP12 may be connected to the bias current IBIAS2, which may be 2 MA. The drain terminal of Mp,4 may be connected to the drain terminal of MNI. The ratio for Mp,2 may be 4y/2y, and the ratio for Mp,4 may be 6 x 4M12M.

Looking to the box corresponding to II, it is shown that I, may be implemented using four n-channel MOS transistors (MNI2, MN14, MN16, MNl8) and a bias current (IBIASI). The source terminals of MN14 and MNl8 may be connected to ground (GND), and the gate terminals of MN14 and MN18 may be connected together. The gate terminal of MN18 may also be connected to the drain terminal of MN18. The source terminal of MN16 may be connected to the drain terminal of MN18, and the drain terminal of MN16 may be connected to the bias current IBIAS1, which may be 2 MA. The gate terminal of MN16 may be connected to the drain terminal of MNl6, as well as the gate terminal of MN 12' The source terminal of MN12 may be connected to the drain terminal of MNl4, and the drain terminal of MN12 may be connected to the source terminal of MN1. As shown in FIG. 6B, the ratios for MN16 and MN18 may be 4µ/2µ, and the ratios for MN12 and MN14 may be 2 x 4µ/2µ.

The unique double source-follower DC level-shifting circuit of the present invention, as shown in FIGS. 5A, 5B, 6A and 6B, provides a significant improvement in the linearity of DC level-shifting circuits for analog-to-digital converter semiconductor devices. FIG. 8 shows an

HSPICE model used to simulate the output response of a circuit according to the present invention. In FIG. 8, VOUTI represents the output of a highly linear source-follower circuit according to the present invention. VOUT2 represents the output of a typical source-follower circuit (see FIG. 2 (prior art)). VOUT3 represents the output of a prior technique for modifying the traditional source-follower circuit (see FIG. 3 (prior art)). Using HSPICE to simulate the response of these circuits to a simulated input voltage, the linearity of the response of these circuits may be compared.

One method of measuring of the linearity of the response of these circuits is to use the normalized maximum deviation of the circuit output from an ideally linear output. FIG. 7 presents a graphical representation of this measure of linearity. In FIG. 7, the vertical axis represents the range from high to low of output voltages (VOUTH to VOUTL), and the horizontal axis represents the range from high to low of input voltages (VINH to VINL). An ideal response is represented in FIG. 7 by a dotted straight line extending diagonally from left to right with a slope of 1. Thus, the DC level-shifting circuit will ideally add a constant voltage value to the input voltage across the expected range of input voltages. The actual response of a circuit is hypothetically pictured in FIG. 7 as the solid curved line shown. The measure of linearity of the actual response can be given by the deviation of the actual response from an ideal response.

A measure of this deviation and the linearity of the circuit may be the maximum normalized deviation of the actual response from an ideal response, according to the following formula: VOUTH- Voum-Voum max VINH (V - VINL Voum I VEH - VOUTH- Voum Using the HSPICE model shown in FIG. 8, the simple source-follower circuit, the prior modified source-follower circuit, and the highly linear source-follower circuit according to the present invention were simulated. Since the LOAD (not shown in FIG. 8) is assumed to draw no DC current, the IDS of the device in the simple source follower is automatically fixed.

Therefore, the linearity of the simple source follower is expected to be as good as the prior modified source-follower, since the IDS of the first source follower device is deliberately fixed.

The following tables represent the simulation results. TABLE 1 includes the results for the circuit according to the present invention. In TABLE 1, the amplitude of VOUT1 is in column 1, and the normalized deviation of VOUT1 from an ideal linear response is in column 2. TABLE 2 (prior art) includes the results for the typical source-follower circuit. In TABLE 2 (prior art), the amplitude of VOUT2 is in column 1, and the normalized deviation of VOUT2 is in column 2.

TABLE 3 (prior art) includes the results for the prior modified source-follower circuit. In TABLE 3 (prior art), the amplitude of VOUT3 is in column 1, and the normalized deviation of VOUT3 is in column 2. TABLE 4 includes the input voltages VIN.

TABLE 1 VOUT1 Normalized Deviation for VOUT1 2.20483554e+00 0.0000e+00 2.25478720e+00 -5.0776e-06 2.30473948e+00 -9.5317e-06 2.35469237e+00 -1.3378e-05 2.40464584e+00 -1.6635e-05 2.45459989e+00 -1.9320e-05 2.50455449e+00 -2.1447e-05 2.55450964e+00 -2.3031e-05 2.60446531e+00 -2.4086e-05 2.65442150e+00 -2.4626e-05 2.70437819e+00 *** -2.4665e-05 *** 2.75433537e+00 -2.4215e-05 2.80429303e+00 -2.3287e-05 2.85425115e+00 -2.1894e-05 2.90420972e+00 -2.0047e-05 2.95416874e+00 -1.7756e-05 3.00412819e+00 -1.5032e-05 3.05408807e+00 -1.1886e-05 3.10404835e+00 -8.3247e-06 3.15400904e+00 -4.3605e-06 3.20397013e+00 0.0000e+00

TABLE 2 (Prior Art) VOUT2 Normalized Deviation for VOUT2 2.20244838e+00 0.0000e+00 2.25227291e+00 -2.2827e-05 2.30210003e+00 -4.3064e-05 2.35192970e+00 -6.0737e-05 2.40176190e+00 -7.5775e-05 2.45159660e+00 -8.8508e-05 2.50143376e+00 -9.8667e-05 2.55127336e+00 -1.0638e-04 2.60111537e+00 -1.1168e-04 2.65095974e+00 -1.1460e-04 2.70080646e+00 *** -1.1518e-04 *** 2.75065548e+00 -1.1345e-04 2.80050676e+00 -1.0944e-04 2.85036028e+00 -1.0319e-04 2.90021600e+00 -9.4741e-05 2.95007387e+00 -8.4129e-05 2.99993386e+00 -7.1392e-05 3.04979592e+00 -5.6570e-05 3.09966003e+00 -3.9703e-05 3.14952613e+00 -2.0833e-05 3.19939419e+00 0.0000e+00 TABLE 3 (Prior Art) VOUT3 Normalized Deviation for VOUT3 2.20743695e+00 0.0000e+00 2.25719291e+00 -2.8628e-05 2.30695199e+00 -5.4117e-05 2.35671418e+00 -7.6487e-05 2.40647945e+00 -9.5757e-05 2.45624779e+00 -1.1195e-04 2.50601917e+00 -1.2509e-04 2.55579358e+00 -1.3519e-04 2.60557099e+00 -1.4227e-04 2.65535138e+00 -1.4636-04 2.70513473e+00 *** -1.4747e-04 *** 2.75492102e+00 -1.4564e-04 2.80471023e+00 -1.4087e-04 2.85450233e+00 -1.3320e-04 2.90429730e+00 -1.2265e-04 2.95409513e+00 -1.0923e-04 3.00389578e+00 -9.2969e-05 3.05369923e+00 -7.3893e-05 3.10350547e+00 -5.2025e-05 3.15331446e+00 -2.7385e-05 3.20312619e+00 0.0000e+00

TABLE 4 VIN <BR> <BR> 1 .00000000e +00 1.05000000e+00 1.10000000e+00 1.15000000e+00 1.20000000e+00 1.25000000e+00 1.30000000e+00 1.35000000e+00 1 .40000000e+00 <BR> <BR> 1 .45000000e+00 <BR> <BR> 1 .50000000e+00 1.55000000e+00 1.60000000e+00 1 .65000000e +00 <BR> <BR> 1 .70000000e+00 <BR> <BR> 1 .75000000e +00 1.80000000e+00 <BR> <BR> 1 .85000000e+00 1.90000000e+00 1.95000000e+00 2.00000000e+00 As indicated by the stars in TABLE 1, the maximum normalized deviation for the circuit according to the present invention was -2.47 x 10-5. In contrast, as indicated by the stars in TABLE 3 (prior art), the maximum normalized deviation for the prior modified source-follower circuit was -1.47 x 104. Also as indicated by the stars in TABLE 2 (prior art), the maximum normalized deviation for the typical source-follower circuit was -1.15 x 10 4. The highly linear source-follower circuit of the present invention, therefore, has a smaller maximum normalized deviation by almost 1/5 compared to the typical circuit and 1/6 compared to the modified circuit. Thus, using the maximum normalized deviation as a measure of linearity, it is shown that the highly linear source-follower DC level-shifting circuit of the present invention provides a significantly higher degree of linearity than does the simple source-follower circuit and the prior modified source-follower circuit. This increased linearity makes the present invention highly advantageous as a DC level-shifting circuit for an analog- to-digital converter semiconductor device.

As a further embodiment of the present invention, additional circuitry may be provided to fix the IDS and VDS of the second source-follower circuit. This circuitry would make the VGs of the second source-follower less variant with the input voltage VIN and would in turn make the VGs of the first source-follower even more linear. This technique could be further cascaded where the (n+ l)th source-follower could make the VGs of the nth source-follower less variant, ultimately resulting in the VGS of the first source-follower becoming even more linear.

Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. For example, the use of n-channel and p- channel devices shown are example arrangements of device types; however, it will be recognized that the present invention is not so limited. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. It is to be understood that the forms of the invention herein shown and described are to be taken as presently preferred embodiments. Equivalent elements or materials may be substituted for those illustrated and described herein, and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention.