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Title:
INSULATED GATE BIPOLAR TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2024/029153
Kind Code:
A1
Abstract:
The present invention provides an IGBT wherein an IE effect is achieved, while suppressing latch-up. The present invention provides an insulated gate bipolar transistor which comprises a first active region (31), a second active region (32), and an inactive region (34) which is arranged between the first active region and the second active region, and in which a plurality of dummy trenches are arranged. An inter-trench region is arranged within a hole accumulation region (36), which is a region between a first boundary gate trench (14gx1) and a second boundary gate trench (14gx2), so as to satisfy the following conditions: a plurality of non-contact inter-trench regions are arranged within the inactive region; at least one contact inter-trench region is arranged within the inactive region; and the non-contact inter-trench regions are not adjacent to each other within the hole accumulation region.

Inventors:
NAGAI TAKAYA (JP)
Application Number:
PCT/JP2023/017802
Publication Date:
February 08, 2024
Filing Date:
May 11, 2023
Export Citation:
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Assignee:
DENSO CORP (JP)
International Classes:
H01L29/12; H01L29/739; H01L29/78
Foreign References:
JP2018182254A2018-11-15
JP2017059725A2017-03-23
JP2019067796A2019-04-25
JP2016082167A2016-05-16
JPH11345969A1999-12-14
Attorney, Agent or Firm:
KAI-U PATENT LAW FIRM (JP)
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