JOINING LAYER OF SEMICONDUCTOR MODULE, SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING SAME

Title:

JOINING LAYER OF SEMICONDUCTOR MODULE, SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING SAME

Document Type and Number:

WIPO Patent Application WO/2019/146587

Kind Code:

A1

Abstract:

Provided is a joining layer (13) that is included in a semiconductor module (10), that is interposed between an electronic component (14) and a substrate (15), and that comprises a CuSn intermetallic compound. This joining layer (13) is configured such that the composition ratio of Sn increases from a central part (13a) thereof toward joining parts (13b, 13c) at ends (14a, 14v) of the electronic component (14). The semiconductor module (10) is produced by interposing a paste containing a Cu-core/Sn-shell-powder between the electronic component (14) and the substrate (15), and applying pressure at 1-30 MPa and applying heat at a temperature of 250-350°C, for 1-10 minutes on the electronic component (14) and/or the substrate (15) in an inert or reducing atmosphere while said paste is kept interposed in place so as to join the electronic component (14) and the substrate (15).

Inventors:

IWATA KOUTARO (JP)
HIGAMI AKIHIRO (JP)
MURAOKA HIROKI (JP)
YAMAGUCHI TOMOHIKO (JP)

Application Number:

PCT/JP2019/001827

Publication Date:

August 01, 2019

Filing Date:

January 22, 2019

Export Citation:

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Assignee:

MITSUBISHI MATERIALS CORP (JP)

International Classes:

H01L21/52; B22F1/00; B22F1/10; B22F1/17; B23K35/14; B23K35/26; B23K35/30; C22C9/02; C22C13/00; H01L23/36

Foreign References:

JP2010179336A	2010-08-19
JP2017177156A	2017-10-05
JP2008221290A	2008-09-25
JP2018009471A	2018-01-18
JP2012074726A	2012-04-12
JP2014199852A	2014-10-23

Other References: