Title:
LAMINATED CERAMIC ELECTRONIC COMPONENT AND MOUNTING STRUCTURE FOR LAMINATED CERAMIC ELECTRONIC COMPONENT
Document Type and Number:
WIPO Patent Application WO/2024/018718
Kind Code:
A1
Abstract:
Provided is a laminated ceramic electronic component that prevents insulation resistance from increasing while ensuring moisture resistance reliability. The laminated ceramic electronic component according to the present invention is characterized by comprising: a laminated body 12 including a plurality of laminated ceramic layers 14 and a plurality of internal electrode layers 16 laminated on the ceramic layers 14, and having a first main surface 12a and a second main surface 12b opposing each other in the lamination direction x, a first side surface 12c and a second side surface 12d opposing each other in the width direction y orthogonal to the lamination direction x, and a first end surface 12e and a second end surface 12f opposing each other in the length direction z orthogonal to the laminating direction x and the width direction y; and a plurality of external electrodes 30, wherein the plurality of internal electrode layers 16 each comprise a first internal electrode layer 16a alternately laminated with a plurality of the ceramic layers 14 and exposed at the first end surface 12e and second end surface 12f, and a second internal electrode layer 16b alternately laminated with a plurality of the ceramic layers 14 and exposed at the first side surface 12c and the second side surface 12d, the plurality of external electrodes 30 each comprise a first external electrode 30a and a second external electrode 30b connected to a first internal electrode layer 16a, and a third external electrode 30c and a fourth external electrode 30d connected to a second internal electrode layer 16b, the first external electrode 30a and the second external electrode 30b each have a base electrode layer 32a, 32b, the base electrode layers 32a, 32b each have a dense region 40a, 40b with a high area ratio of conductive components and a sparse region 42 with a lower area ratio of conductive components than the dense regions 40, and the dense regions 40 are located farther to the laminated body 12 side than the sparse regions 42.
Inventors:
USUI KAZUNORI (JP)
SAWADA TAKASHI (JP)
SAWADA TAKASHI (JP)
Application Number:
PCT/JP2023/016529
Publication Date:
January 25, 2024
Filing Date:
April 26, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G4/30; H01G4/35
Foreign References:
| JP2018207091A | 2018-12-27 | |||
| JP2020088191A | 2020-06-04 | |||
| JP2018163934A | 2018-10-18 | |||
| JP2018170355A | 2018-11-01 |
Attorney, Agent or Firm:
OKADA, Masahiro (JP)
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