Low cost digital real-time link system.

The invention relates to a distributor for synchronized digital signals representing realtime audio data relating to a number of audio elements in a network. For instance, a low cost digital loudspeaker link system may utilize a low cost Ethernet physical layer components but still achieve real-time transportation of digital PCM audio data and matching control- and status information.

A modern home entertainment centre comprises audio elements that may be termed, respectively, an audio master, a TV-set or loudspeaker, the number and distribution of each being driven by the end user. Various signal distribution schemes for audio are well known, from speaker cables at the output power level, via line-level cable distribution, optical distribution and more recently cable network distribution. The latter are best known for use with intra-and extranets and will send audio data as packets, because many distribution protocols are packet switching protocols. However, in a home environment with multiple loudspeakers it is very important to preserve the established phase relationships between various signal channels, because that is essential to recreate the spatial information required for e.g. 5.1 listening. Furthermore, if a number of rooms are supplied simultaneously, it would not function well if neighbouring rooms were provided with sound with different delays, because strange echo effects would occur when sound from both rooms are heard.

It is the purpose of the invention to provide a distribution system for signals of the above-mentioned type in which any timing errors are avoided and which may be established irrespective of the physical layout of a cable or other network.

This is obtained in a distributor according to the invention that is particular in that it comprises a physical layer with a physical topology and a logical layer with a logical topology according to a communications protocol. The logical topology of the link system is basically: a daisy chained ring. The term "logical topology" is used here as an abbreviation for the data flow trough the system, while the term "physical topology" is

used as an abbreviation for the actual topology of how the system is connected with physical cables.

In a preferred embodiment said physical layer and said logical layer are independent.

According to an advantageous embodiment of the invention the logical topology comprises two full duplex communications channels for each element in the system.

Because every audio master or loudspeaker has two full duplex communication channel accesses to the cable it is possible to achieve a logical daisy chained ring architecture even though the physical wiring is done in star connection manner. Having the logical topology as a daisy-chained ring architecture has clear advantages in securing the distribution of synchronization information. Every node in the ring can always gain access to the network and forward data frames to the following node. This guaranteed dataflow thereby ensures a more deterministic transportation of the synchronization information than could be achieved in a traditional switched star-coupled network.

According to a further advantageous embodiment of the invention, the signals distributed are provided with a data structure, in which control and status information is embedded in the audio data stream. This has the clear advantage that synchronization between channels may be obtained with a precision determined by the data rate and not by a delay due to a packet structure.

According to a further advantageous embodiment of the invention any element in the system may take the role of synchronizing element.

According to a further advantageous embodiment of the invention the signals distributed have a structure such that synchronization information may be extracted from the data streams.

According to still further advantageous embodiment of the invention, local signal processing is clocked by the corresponding local audio element and in that the signals are re-synchronized by means of a Phase-Locked Loop (LLP).

An advantageous device for use in an audio element according to the present invention is particular in that it comprises a transmission interface for synchronous audio data and a transmission interface for asynchronous control and status data.

The transport media may be standard Ethernet style twisted pair cables (e.g. 100BaseTX lOOMbit). Every device in the link system, Audio master, TV-set, or loudspeaker, has two Ethernet physical layer ICs (PHY's) enabling 2 full duplex communication channels on the media using 2 standard Ethernet Mil interfaces. The protocol layer above the Mil interface layer is handled by an FPGA device.

It should be noted that due to the separation into a physical and a logical layer, the physical layer may have any structure as long as it can handle the data rate. For instance, an optical fibre network or an infrared data communication system may be equally useful according to the present invention as will a wireless data communication system.

In the following, a number of terms will be used for various elements in the system:

Node : Audio control centre, TV-set, Loudspeaker or repeater unit (including the

Distributor interface). Mil : Media Independent Interface

PCM : Pulse code modulation

FPGA : Field programmable gate array.

IC : Integrated Circuit

PHY : Ethernet physical layer IC DSP : Digital Signal Processor

Host : Processor hosting the Distributor interface.

PLL : Phase locked loop.

FEC : Forward Error correction.

The invention will be further described with reference to the drawings, in which:

Fig. 1 shows an embodiment of the invention regarding a home cinema Surround setup,

Fig. 2 shows a similar embodiment of a home cinema Surround setup,

Fig. 3 shows a distributor interface according to an embodiment of the invention,

Fig. 4 shows a sketch of the basic building blocks within the FPGA part of the interface,

Fig. 5 shows a block schematic for some of the logical blocks of the Mil subsystem, handling the high speed signals towards Mil interfaces, inside the FPGA,

Fig. 6 shows the schematic structure of the distributor frame format according to the invention,

Fig. 7 shows a block diagram for the audio clock master synchronization information transmitter, and

Fig. 8 shows a block diagram for the audio synchronisation information receiver and audio clock regenerator in the slave devices.

Fig. 1 shows a typical home cinema Surround setup. The somewhat speckled line indicates how the daisy chained ring architecture is obtained by using the 2 full duplex interfaces in the TV-set and the L,R loudspeakers. At the same time, the Ls ₅ Rs loudspeakers placed at the end of the physical chain only uses 1 full duplex interface.

Reference is made to Fig. 2, in which is shown a system comprising 5 units, such as speakers. Those should be considered as slave-units. The repeater should be seen as a connection and nothing else. It will not have any audio functionality, and it will not have an address. The Master-unit is the controller of all activities in the logical layer. It transmits a frame rate of 8 kHz, containing both sound data and control data. See Fig. 6 for one embodiment of a frame format structure. The frame transmitted will be transmitted from the master, sent through all the slave-units, and then received by the Master again. Contained in this frame is also a counter, which is incremented by each slave-unit, this will tell the Master-unit how many slave-units are in the system, when it receives the data string again. This value is saved in a register in the master in order that the Master software can read this value, and it then knows how many slave-units there

are in the system. A slave-unit that is not configured will set its address to be equal to the counter value it puts into the frame, when it forwards the frame to the next slave- or Master-unit. As long as the slave-unit is not configured by the micro-processor in the slave-unit, it has to update the address to be equal to the counter-value. After a configuration, the slave-unit may no longer on its own accord change an address.

Various situations arise:

Power Up Configuration without known slave-units, i.e. a power-up configuration, in which the Master and the slave-units have never been configured before. When the system is powered up, the master commences transmitting frames with no audio data, and no control information. But this tells the Master how many slave-units there are connected. In the above situation, the Master has 5 slave-units connected. The slave-unit with the "1", is the first slave-unit in the path, and the slave-unit with the "2", is the next, and so on.

Power Up Configuration with blown slave-units, i.e. a power-up, and the master knows some of the slave units, and some of the slave-units are new. When the system is powered up, the master commences transmitting frames with no audio data, and no control information. But this tells the Master how many slave-units there are connected. In the above situation, the Master has 5 slave-units connected. The slave-unit with the "1", is the first slave-unit in the path, and the slave-unit with the "2", is the next, and so on. The Master has slave-unit 4 and 5 in the config-list from before powering down. Slave-unit 4 had address 1, and slave-unit 5 had address 2.

Connecting new slave-units while running, i.e. what will happen when the user connects new slave-units while the system is not powered down. The Master and slave-units named 4 and 5 are running. Then the user connects the repeater with slave-units 1, 2 and 3 connected, to the Master. The Master will start transmitting the frames through the repeater to "1", then "2", and then "3", and after this "4" and "5". Slave-unit 4 has address 1, and slave-unit 5 has address 2. The Master will now inform the master software that there are 5 slave-units connected, and the software has to do a configuration.

Connecting already configured slave-units while running, i.e. what will happen if the user has disconnected some slave-units, and then connects them again, without powering the units off. The Master and slave-units named 4 and 5 are running. Then the user connects the repeater with slave-units 1, 2 and 3 connected, to the Master, which are already configured. The Master will start transmitting the frames through the repeater to "1", then "2", and then "3", and after this "4" and "5". Slave-unit 1 has address 1, and slave-unit 2 has address 2, and so on. The Master will now inform the master software that there are 5 slave-units connected, and the software has to do a configuration.

Further situations will be treated in a similar way by the control logic, such as:

Disconnecting already configured slave-units

Too many slave-units in Master Config-list

Fig. 2 more specifically shows another example of a home cinema Surround setup than that of Fig. 1. In this case the physical wiring is done in essentially a star connection. The central connection unit is a specially designed repeater device. This kind of setup would be preferred in situations where the cable wiring is done as a part of the permanent technical installation in the house. The repeater device would in that case be placed as part of the hidden technical installation.

In the embodiment described the Distributor is limited to a total of 32 nodes in the system. Data frames are sent round the logical ring. Every device is allowed to insert data in the frames at their own location assigned by the "link master". The repetition of frames in the devices is done with very low latency. Hence, the total circulation delay in the ring will be less than 20 μs (approximately one audio sample period at 48kHz sample rate) taking into account both repeater delays and delays due to physical cable lengths. In many applications the phase difference in the audio presentation due to the delay around the ring would be acceptable. But the repeater delay is static and deterministic, and the number of repeater hubs to any point in the ring is well known by the link master. Thus a delay compensation system is built in, enabling phase alignment in the system below 1 μs.

Every node in the system has a Distributor interface as shown in Fig. 3. The figure shows how the logical daisy chained ring architecture is achieved using a combination of one and two duplex interfaces in a star topology. The application interface consists of a synchronous serial audio interface for PCM audio and an asynchronous serial interface for control and status information. The synchronous interface is an I2S-like interface, which is used for serially transporting PCM audio between the host application processor and the Distributor interface. The asynchronous interface is also basically a synchronous serial interface, but the interface is used in an asynchronous manner, which is only active when control and status information has to be exchanged between the Distributor interface and the application processor. PHYl and PHY2 as shown in Fig. 3 are standard Ethernet lOOMbps PHYs. The PHYs is connected trough a galvanic separation stage to standard RJ45 connectors. The cables used are standard Ethernet style twisted-pair cables.

AU electrical signalling and communication left of the Mil interface shown in Fig. 3 is obtained using standard 100Base-TX lOOMbps Ethernet physical layer protocol. This standardized part of the Distributor will therefore not be explained further in this document.

Fig. 4 shows the basic buildings blocks within the FPGA part of the interface. The Mil subsystem handles the high speed interfacing towards the Mil interface. PHYl and PHY2 as shown in Fig. 3 are clocked by a local crystal oscillator running at 25 MHz. This clock signal is also fed to the FPGA to be used for clocking the Mil subsystem.

The Error correction subsystem uses a Forward Error Correction (FEC) algorithm to correct possible errors should they occur. The Error correction subsystem is optional. The Audio subsystem handles the audio buffering and formatting between the high speed Mil interface and the much slower I2S-like interface toward the application processor. The Sync subsystem is used by the audio subsystem to recover the audio sample clock of the incoming audio data stream. The synchronization information used for that purpose is embedded in every incoming data frame. The sync subsystem is accompanied by external analogue components to form a PLL circuitry used for recovering and cleaning the audio sample clock. The control subsystem handles control and status information buffering and formatting between the Mil subsystem and the

application interface.

In Fig. 5 is shown a more detailed block diagram of an embodiment of the Mil subsystem. The Mil subsystem receives the incoming data 4 bit at a time from the Mil interfaces. It is capable of retransmitting the data on the TX part of the other Mil interface. The total latency through the in and out buffers in the chain is only two 25 MHz clock cycles. Hence the repeater latency trough the Mil subsystem will only be approximately 80 ns. The selection logic between the input and output buffers makes it possible for the Mil subsystem to insert data in the data stream. The controller controls the repetition and insertion of data. It holds counters that count Phy elk periods throughout the frame period. These counters get synchronized by the RX data valid signal's rising edge, which indicates a new frame start. It also controls the RX and TX data buffers.

The Distributor protocol hierarchically above the Mil interface is as described in the present text. In the above-mentioned examples the TV-set will be the "link master" in the system. In the following the terminology "link master" and "audio clock master" will be used. The "link master" is the initiating device on the link system. It would also be the primary audio clock master. It is the device that initiates the transmission of data frames around the chain. The term "audio clock master" is used for the device that inserts synchronisation information into the data frames related to a particular audio data stream. In the simple case of only one audio clock master the two terms would always refer to the same device, as the primary audio clock master will always get the task being the "link master". The Distributor protocol uses a fixed frame rate architecture with a frame frequency of 8 kHz, as sketched in Fig. 6. The "link master" sends out frame on a continuous basis. That means that every 125 μS the link master initiates a new frame start transmission toward the nearest neighbour in the logical ring.

Every device in the ring is capable of retransmitting the frame to the next neighbour node in the ring.

Every frame consists of 3125 times 4 bit. The frame is divided into a fixed part and a dynamic part. In the fixed part of the frame every location has a predefined purpose. The first field (S) is where the primary audio clock master insert its synchronization

information. The (MA) field is used by the audio clock master to transmit up to 16 channels of 24 bit audio. The number of audio samples for each channel varies from frame to frame as the audio sampling rate is asynchronous to the frame rate. The number of average audio samples for each channel is flexible. It depends on the audio sampling rate. E.g. 96 kHz audio would require on average twice as many samples in each frame as 48kHz audio. The Master control field (M. Cntl.) is used by the master to insert control data intended for the slave devices. The master control field is further divided into address and data fields, not explained further in this document.

The (S1-S32) fields are assigned to the slaves. Each slave gets it own field assigned. ^' Each slave can freely at any time insert control data into its own (Sx) field. The higher level protocol defining the content of the data inserted into these fields will not be described further in this document.

The remainder of the frame is used for dynamic allocation controlled by the link master. Using this dynamic part of the frame it is possible for the link master to allow slaves to e.g. transmit audio and synchronization information on the link. This dynamic allocation opens the possibility of having multiple secondary audio clock masters in the system without the need for predefined fields for this purpose.

At the end of each frame is inserted a small gap. The gap is long enough to absorb differences in frame length due to skewedness between the different local phy elk oscillators in the ring chain.

The Distributor system is based on having one primary audio clock master. In Fig. 7 is shown a block diagram for the audio clock master synchronisation information transmitter.

The audio clock master measures the audio sample clock relative to its PHY elk. This PHY elk is also used at frame synchronizer trough the whole link system. The audio sample clock is divided in the DIV block by a factor of 8. E.g. 44.1 kHz audio sample rate would be divided by DIV to a 5.5125 kHz signal. Every time the sync controller sees a rising edge on this signal it latches the 12 bit Master Counter value. At the end of each frame period this value is transferred to the TX Latch, ready for transmission in the

following frame. If no rising edge is found the valid bit is held low to indicate that no sync pulse should be generated in this frame period.

By distributing the explained relative measure using the (S) field in the protocol frame, all the slaves can use this for regeneration of the audio clock.

In Fig. 8 is shown a block diagram for the audio synchronisation information receiver and the audio clock regenerator within the slave devices.

The slave counters count on their local PHY clock. But every incoming frame resets this counter. This resetting serves to ensure that the counters do not drift with respect to each other because of any skewedness between PHY clocks.

The count value from the (S) field is latched in one frame period and used for synchronisation in the following frame period. The count value indicates the placement of a sync pulse within that frame. If the valid bit from the (S) field indicates that the count value is invalid, there will be no sync pulse in that frame period.

The Distributor synchronisation system can only handle generation of one sync pulse in each frame period. Thus the divider (DIV) in Fig. 7 will always divide the audio clock rate down to a frequency below the 8 kHz frame rate used.

The PLL regenerates the audio clock from the sync pulses.

It will be realized that the logical and physical layers are completely independent, so that if the physical network is not a daisy-chain, the logical layer still performs as a daisy chain of the same type as for any other physical configuration. The logical network is self-configuring in this respect.

A low cost digital loudspeaker link system has hence been realized, which utilizes low cost Ethernet physical layer components to achieve real-time transportation of digital PCM audio data and matching control- and status information. It is intended as link between an audio control centre, TV-set products and a number of active powered loudspeakers in a home audio setup. The transport media is standard Ethernet style

twisted-pair cables (100Base-TX lOOMbit). Every device in the link system, Audio master, TV-set or loudspeaker, has two Ethernet physical layer ICs (PHY's) enabling 2 full duplex communication channels on the media using 2 standard Ethernet Mil interfaces. The protocol layer above the ME interface layer is handled by an FPGA device.

The protocol according to the invention is designed in a manner that makes it possible to embed synchronization information in-between data. The synchronisation information makes it possible to regenerate an audio sample clock in the receiving end. The system is based on having one "link master" which is also the primary "audio clock master". But the system is not limited to having only one audio clock master, but can easily be expanded to more audio clock masters in the same link system.

The foregoing description of the specific embodiments will so fully reveal the general nature of the present invention that others skilled in the art can, by applying current knowledge, readily modify or adapt for various applications such specific embodiments without undue experimentation and without departing from the generic concept, and therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. The means, materials, and steps for carrying out various disclosed functions may take a variety of forms without departing from the invention.

Thus, the expressions "means to ... " and "means for ...", or any method step language, as may be found in the specification above and/or in the claims below, followed by a functional statement, are intended to define and cover whatever structural, physical, chemical, or electrical element or structure, or whatever method step, which may now or in the future exist which carries out the recited functions, whether or not precisely equivalent to the embodiment or embodiments disclosed in the specification above, i.e., other means or steps for carrying out the same function can be used; and it is intended that such expressions be given their broadest interpretation.