Title:
MASK PATTERN DESIGNING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME
Document Type and Number:
WIPO Patent Application WO/2008/023660
Kind Code:
A1
Abstract:
A time required for optical proximity correction (OPC) processing in mask pattern
designing is reduced. A mask pattern is formed by laying out cells to which the
OPC processing has been previously performed, then, at the time of finely adjusting
a correction quantity for the OPC, for each cell, calculation for the fine adjustment
is performed only for a region where an adjustable region of the cell itself and
surrounding regions of other cells adjacent to the adjustable region overlap
each other. Thus, a range of performing the fine adjustment of an OPC pattern (an
area of a region for which the calculation is required) can be reduced. Since the
mask pattern can be efficiently designed, processing time and processing cost
required for the mask pattern designing can be remarkably reduced.
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Inventors:
NOSATO HIROKAZU (JP)
MATSUNAWA TETSUAKI (JP)
TAKAHASHI EIICHI (JP)
SAKANASHI HIDENORI (JP)
HIGUCHI TETSUYA (JP)
MATSUNAWA TETSUAKI (JP)
TAKAHASHI EIICHI (JP)
SAKANASHI HIDENORI (JP)
HIGUCHI TETSUYA (JP)
Application Number:
PCT/JP2007/066108
Publication Date:
February 28, 2008
Filing Date:
August 20, 2007
Export Citation:
Assignee:
NAT INST OF ADVANCED IND SCIEN (JP)
NOSATO HIROKAZU (JP)
MATSUNAWA TETSUAKI (JP)
TAKAHASHI EIICHI (JP)
SAKANASHI HIDENORI (JP)
HIGUCHI TETSUYA (JP)
NOSATO HIROKAZU (JP)
MATSUNAWA TETSUAKI (JP)
TAKAHASHI EIICHI (JP)
SAKANASHI HIDENORI (JP)
HIGUCHI TETSUYA (JP)
International Classes:
G03F1/36; G03F1/68; G03F1/70; G06F17/50; H01L21/027
Domestic Patent References:
| WO2006104244A1 | 2006-10-05 |
Foreign References:
| JP2005084101A | 2005-03-31 | |||
| JP2002055431A | 2002-02-20 | |||
| JPH1032253A | 1998-02-03 | |||
| JP2000314954A | 2000-11-14 | |||
| JPH08254812A | 1996-10-01 | |||
| JP2006276279A | 2006-10-12 |
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