METHOD FOR MANUFACTURING REVERSE-BLOCKING SEMICONDUCTOR ELEMENT

Title:

METHOD FOR MANUFACTURING REVERSE-BLOCKING SEMICONDUCTOR ELEMENT

Document Type and Number:

WIPO Patent Application WO/2012/099080

Kind Code:

A1

Abstract:

The present invention is a method for manufacturing a reverse-blocking semiconductor element wherein a tapered channel is formed. A back surface collector layer is formed and a discrete layer (4) is formed on the side edge surfaces of the tapered channel by furnace annealing and laser annealing following ion implantation in the back surface and tapered channel. Thus, even in a manufacturing method having a manufacturing step wherein a diffusion layer, which is formed by forming the tapered channel, ion implantation, and annealing on the side edge surfaces thereof, is formed into a discrete layer (4) for twisting and extending the end edge of a reverse-voltage resistant pn junction on the surface, reverse voltage resistance can be assured and reverse bias leak current can be reduced.

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Inventors:

NAKAZAWA HARUO (JP)

Application Number:

PCT/JP2012/050760

Publication Date:

July 26, 2012

Filing Date:

January 16, 2012

Export Citation:

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Assignee:

FUJI ELECTRIC CO LTD (JP)
NAKAZAWA HARUO (JP)

International Classes:

H01L21/336; H01L21/265; H01L21/76; H01L29/739; H01L29/78

Foreign References:

JP2006303410A	2006-11-02
JP2005268487A	2005-09-29
JP2003059856A	2003-02-28

Attorney, Agent or Firm:

SAKAI, AKINORI (JP)
Akinori Sakai (JP)

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