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Title:
MANUFACTURE OF INSULATED GATE TYPE FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH022170
Kind Code:
A
Abstract:

PURPOSE: To avoid the floating state of gate electrodes by a method wherein a plurality of the adjacent gate electrodes having different work functions corresponding to the difference in impurity concentration are exposed and a metal or metal-semiconductor compound film 17 is selectively built up on the surfaces of the gate electrode materials only.

CONSTITUTION: A silicon oxide film 18 for element isolation is formed on a silicon substrate 11 and a gate oxide film 12 formed on an element forming region and a polycrystalline silicon film 19 is built up over the whole surface. Phosphorus contained in phosphorus glass of a spacer 14 is diffused into the polycrystalline silicon film 19 to make only both the side wall parts of the polycrystalline silicon film 19 n-type. With this constitution, a plurality of adjacent (n+-type, p+-type and n+-type) gate electrodes 13 having different work functions correcponding to the difference in impurity concentration are formed. As the gate electrodes 13 having different work functions corresponding to the difference in impurity concentration are mutually short-circuited by a selective silicide forming method, the floating state of the gate electrodes 13 can be avoided.


Inventors:
IZAWA TETSUO
Application Number:
JP14583988A
Publication Date:
January 08, 1990
Filing Date:
June 15, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L29/78; H01L21/336; H01L29/49; (IPC1-7): H01L21/336; H01L29/78; H01L29/784
Attorney, Agent or Firm:
Motoki Hisagi (1 outside)