Title:
NONVOLATILE SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
WIPO Patent Application WO/2006/120903
Kind Code:
A1
Abstract:
A nonvolatile semiconductor storage device is provided with a memory cell selecting circuit which selects a selected memory cell (M0) from a memory cell array (3); and a write voltage applying circuit, which applies a row write voltage and a column write voltage to a selected word line and a selected bit line, respectively, and applies a row write blocking voltage and a column write blocking voltage to an unselected word line and an unselected bit line, respectively, and applies a write voltage sufficient for writing only on both ends of the selected memory cell (M0). The write voltage applying circuit applies a write compensating voltage, which has a polarity opposite to that of the voltage applied on the both ends of the unselected memory cells (M1, M2) other than the selected memory cell (M0), on both ends of the unselected memory cells (M1, M2), while the write voltage is applied to the selected memory cell (M0).
Inventors:
SHIMAOKA ATSUSHI (JP)
KAWAZOE HIDECHIKA (JP)
TAMAI YUKIO (JP)
KAWAZOE HIDECHIKA (JP)
TAMAI YUKIO (JP)
Application Number:
PCT/JP2006/308730
Publication Date:
November 16, 2006
Filing Date:
April 26, 2006
Export Citation:
Assignee:
SHARP KK (JP)
SHIMAOKA ATSUSHI (JP)
KAWAZOE HIDECHIKA (JP)
TAMAI YUKIO (JP)
SHIMAOKA ATSUSHI (JP)
KAWAZOE HIDECHIKA (JP)
TAMAI YUKIO (JP)
International Classes:
G11C13/00; H01L27/10
Foreign References:
| JP2005032401A | 2005-02-03 |
Attorney, Agent or Firm:
Masaki, Yoshifumi (3-6 Imabashi 4-chome, Chuo-k, Osaka-shi Osaka 42, JP)
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