Title:
PROCESSOR-MEMORY SYSTEM
Document Type and Number:
WIPO Patent Application WO2003038623
Kind Code:
A3
Abstract:
The invention relates to a processor-memory system (1) comprising a processor (2), a data bus (3) and a memory unit. The memory unit has a plurality of working memories (4, 5, 6) and a plurality of cache memories (7, 8). A cache memory (7, 8) is assigned at least partly to the working memories (4, 6). The data bus (3) is arranged between the processor (2) and the memory unit.
Inventors:
POTT RUEDIGER (DE)
Application Number:
PCT/DE2002/003022
Publication Date:
October 09, 2003
Filing Date:
August 19, 2002
Export Citation:
Assignee:
INFINEON TECHNOLOGIES AG (DE)
POTT RUEDIGER (DE)
POTT RUEDIGER (DE)
International Classes:
G06F12/04; G06F12/0802; G06F12/0862; G06F12/0888; (IPC1-7): G06F12/08; G06F12/04; G06F12/12
Foreign References:
| FR2627298A1 | 1989-08-18 | |||
| EP0843261A2 | 1998-05-20 | |||
| US5696929A | 1997-12-09 | |||
| US5936971A | 1999-08-10 |
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