RADIX-4 ENCODING AND DIFFERENTIAL WEIGHT BASED MULTIPLY-ACCUMULATE CIRCUIT

Title:

RADIX-4 ENCODING AND DIFFERENTIAL WEIGHT BASED MULTIPLY-ACCUMULATE CIRCUIT

Document Type and Number:

WIPO Patent Application WO/2020/238889

Kind Code:

A1

Abstract:

Disclosed is a radix-4 encoding and differential weight storage based multiply-accumulate circuit, comprising an input data encoding circuit (1), a differential weight storage circuit (2), an integral calculation circuit (3) and a differential ADC circuit, wherein an output end of the input data encoding circuit (1) passes through the differential weight storage circuit (2) and the integral calculation circuit (3) in sequence and is then connected to the differential ADC circuit, and the differential ADC circuit outputs a multiply-accumulate result; and original input data is encoded by the input data encoding circuit (1) and then multiplied by a weight value stored in the differential weight storage circuit (2), a positive value and a negative value of each multiplication result are respectively accumulated by means of the integral calculation circuit (3), and then analog-to-digital conversion is carried out on the difference between positive and negative value accumulation results by means of the differential ADC circuit, so that a final multiply-accumulate result is obtained. The multiply-accumulate circuit has the advantages of being small in area, high in calculation speed, low in power consumption, etc., can be used for a neuromorphic chip, and can particularly achieve large-scale parallel calculation in an edge computing device with a relatively high energy consumption requirement.

More Like This:

WO/2020/226634	DISTRIBUTED SYNCHRONOUS TRAINING ARCHITECTURE USING STALE WEIGHTS
JPH10260817	SEMICONDUCTOR ARITHMETIC CIRCUIT, AND DTA PROCESSOR
JP7118930	Spiking neural network device and its learning method

Inventors:

HUANG KEJIE (CN)
XIAO RUI (CN)
SHEN HAIBIN (CN)

Application Number:

PCT/CN2020/092286

Publication Date:

December 03, 2020

Filing Date:

May 26, 2020

Export Citation:

Click for automatic bibliography generation Help

Assignee:

UNIV ZHEJIANG (CN)

International Classes:

G06N3/063; G06F7/544

Foreign References:

CN110209375A	2019-09-06
CN109146070A	2019-01-04
CN102662624A	2012-09-12
CN109196528A	2019-01-11
CN101010665A	2007-08-01
US5796645A	1998-08-18

Attorney, Agent or Firm:

TSINGYIHUA INTELLECTUAL PROPERTY LLC (CN)

Download PDF:

View/Download PDF PDF Help

Previous Patent: INTERFERENCE PROCESSING METHOD AND DEVICE

Next Patent: INFORMATION PROCESSING METHOD AND DEVICE