Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/018715
Kind Code:
A1
Abstract:
A semiconductor device (1) comprises: a semiconductor layer (40) that is rectangular in a plan view; a first vertical MOS transistor (10) formed in a first region (A1) of the semiconductor layer (40); and a second vertical MOS transistor (20) that is formed in a second region (A2) adjacent to the first region (A1) in a plan view. In a plan view, the first and second regions (A1, A2) are the one and the other that divide the area of the semiconductor layer (40) into two equal parts. The shape formed by a first gate wiring (114) and a first gate electrode (19) provided in the first region (A1) and the shape formed by a second gate wiring (124) and a second gate electrode (29) provided in the second region (A2) are not line-symmetrical to each other if the boundary line between the first region (A1) and the second region (A2) is the symmetry axis, and are not point-symmetrical to each other if the center of the semiconductor layer (40) is the symmetry center.
Inventors:
HAYASHI MASAHIRO
INOUE TSUBASA
INOUE TSUBASA
Application Number:
PCT/JP2023/016405
Publication Date:
January 25, 2024
Filing Date:
April 26, 2023
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
H01L29/78
Foreign References:
| JP2022026643A | 2022-02-10 | |||
| US20110233605A1 | 2011-09-29 | |||
| JP2019161168A | 2019-09-19 | |||
| JP2005302952A | 2005-10-27 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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