Title:
SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2023/226071
Kind Code:
A1
Abstract:
The present disclosure relates to a semiconductor structure and a preparation method therefor. The preparation method comprises: providing a substrate, and sequentially forming a bit line contact structure and a bit line on the substrate, wherein the bit line comprises a connection layer connected to the bit line contact structure; etching back side walls of the bit line contact structure and the connection layer; and forming a first silicide layer that covers the side wall of the bit line contact structure, and a second silicide layer that covers the side wall of the connection layer. By means of the present disclosure, the contact resistance between the bit line contact structure and the bit line, and the parasitic capacitance between the bit line contact structure and an adjacent conductive structure can be reduced, such that the electrical performance of the semiconductor structure is improved, thereby improving the use reliability and yield of the semiconductor structure.
Inventors:
WU TIEH-CHIANG (CN)
ZHU LINGXIN (CN)
ZHU LINGXIN (CN)
Application Number:
PCT/CN2022/096596
Publication Date:
November 30, 2023
Filing Date:
June 01, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/8242; H01L27/108
Foreign References:
| CN111584432A | 2020-08-25 | |||
| CN1146072A | 1997-03-26 | |||
| CN109003938A | 2018-12-14 | |||
| US20060068545A1 | 2006-03-30 |
Attorney, Agent or Firm:
ADVANCE CHINA IP LAW OFFICE (CN)
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