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JP2671872B2 |
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JP2674096B2 |
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JPH09282401A |
To provide the ground height slide rule with which the ground height of a container and the ground height of a truck can easily and precisely be found irrelevantly to the kind of the container. One of upper and lower fixed rules 10 and 1...
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JPH09282402A |
To realize addition, subtraction and absolute value arithmetic by a small circuit scale by expressing a signal by the sum or the difference of currents flowing through two signal wires. The two signal wires are assigned to the signal. Wh...
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JP2670555B2 |
PURPOSE:To give a learning and to simplify a circuit configuration by using an element to generate an output according to the level of an input signal and making variable the input/output characteristics of this element. CONSTITUTION:Dec...
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JPH09510808A |
PCT No. PCT/EP94/04331 Sec. 371 Date Sep. 10, 1996 Sec. 102(e) Date Sep. 10, 1996 PCT Filed Dec. 28, 1994 PCT Pub. No. WO95/26528 PCT Pub. Date Oct. 5, 1995The analog fuzzy logic controller includes a fuzzification circuit by which the p...
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JP2668844B2 |
PURPOSE: To control the shape of a material to be rolled more excellently than to control the shape of a material to be rolled of a Sendzimir mill by an existing neural network and a fuzzy inference. CONSTITUTION: Part lowest in steepnes...
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JP2668607B2 |
PURPOSE: To directly generate a membership function from a digital value by generating positive and spare analog amounts by inputting the high-order bit of the digital value to a decoder and the low-order bit to a D/A converter, and sele...
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JP2669330B2 |
PURPOSE: To provide the differential circuit which exhibits exponent characteristics against a differential input voltage by driving one transistor, between a pair of transistors consisting of a differential pair, by a constant current a...
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JP2669397B2 |
PURPOSE: To expand an input voltage range having excellent linearity and to make it possible to drive this bipolar multiplier at low voltage by adding and impressing one of the normal and reverse phases of 1st and 2nd differential amplif...
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JP2667673B2 |
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JP2667327B2 |
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JP2666830B2 |
The neural computing paradigm is characterized as a dynamic and highly parallel computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivit...
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JP2663995B2 |
A triangular scalable neural array processor unit for use in a neural network and having multipliers, communicating adder trees, sigmoid generators, and a reverse feedback loop for communicating the output of a sigmoid generator back to ...
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JP2550943Y2 |
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JP2662559B2 |
The invention relates to a semiconductor device comprising: an MOS transistor having a floating gate (1203) formed on a substrate, and a first electrode (1201) with a capacitive coupling coefficient C1 and at least one further electrode ...
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JP2663979B2 |
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JP2663996B2 |
A triangular scalable neural array processor unit for use in a neural network and having multipliers, communicating adder trees, sigmoid generators, and a reverse feedback loop for communicating the output of a sigmoid generator back to ...
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JP2660694B2 |
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JP2661394B2 |
A four quadrant analog multiplier circuit including first to third squaring circuits 1 to 3 each of which is composed of first and second differential circuits each of which is formed of first and second MOS transistors M1 and M2, M3 and...
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JPH09265463A |
To converge the learning of a hierarchical neural network (N.N) in an optimum minimum value state by evading a local minimum value state in a learning process. Learning data X to be learned are inputted to an N.N operation means 1, which...
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JPH09265504A |
To output a true resolver angle of high prevision even with a request signal which is asynchronous with sampling pulses by estimating the true resolver angle from a specific expression when a request signal is inputted in real time in en...
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JPH09259205A |
To execute a product sum operation at a high speed with less hardware amount. Analog voltages Xi respectively corresponding to the respective elements of a first input data string are inputted through input terminals 11-1n to capacitance...
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JPH09259204A |
To facilitate overtime calculation by providing a 1st cursor of length of basic work time and a 2nd cursor which is graduated with overtime. A main body part 2 is continuously graduated with time, and time gradations are given on the sur...
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JPH09261689A |
To obtain a chroma signal over a broad frequency band while compressing information quantity in the transmission and recording of a component image signal where a frequency band of the chroma signal is compressed to about 1/2 with respec...
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JPH09259206A |
To execute discrete cosine transformation at a high speed. The analog input signals x(0)-x(7) of eight points are respectively inputted through capacitors d0-d6 to the positive input terminal (+) or negative input terminal (-) of neural ...
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JP2659867B2 |
A neural network shell (32) has a defined interface (31) to an application program. By interfacing with the neural network shell, any application program becomes a neural network application program. The neural network shell contains a s...
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JPH09245110A |
To obtain a semiconductor integrated circuit with a hand shaking function with a smaller number of elements and a less chip area by connecting the output of threshold circuit to at least one input electrode in the threshold circuit provi...
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JP2654155B2 |
PURPOSE:To easily select the analog input signals which are decided based on the ranking of their values by inhibiting the supply of the input signal decided as the highest signal level via a neural net in the next decision. CONSTITUTION...
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JP2651635B2 |
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JPH09237307A |
To obtain a neuron computer chip having a high degree of integration and low power consumption by providing the semiconductor device with a 4th main electrode having a function for controlling a control method for a current flowing betwe...
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JPH09238032A |
To realize a low voltage operation and a complete linear operation with a simple circuit configuration by realizing a floating resistor equivalently and adopting a current mirror circuit for an output. A constant current source I0 is con...
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JPH09231295A |
To suppress the deviation in an integral waveform caused by the parasitic capacity and to obtain a correct integral waveform by turning on only the specific switching elements in an integral period and setting a differential amplifier ci...
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JP2648386B2 |
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JP2646900B2 |
PURPOSE:To easily determine a draft schedule, and to execute a stable opra-tion by learning an operator set value of the draft schedule by using a multi-layer neural network. CONSTITUTION:An operator set value of a draft schedule is bare...
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JPH09223018A |
To explain the reason of an operation that is carried out via a neural network in response to every fuzzy rule by finding the input/output corresponding relation between the specific input and output ranges and extracting this correspond...
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JP2643516B2 |
A logarithmic amplifier circuit has n (n>1) stages of differential amplifiers, n+1 in number, of rectifying circuits, a differential pair of bipolar transistors having different emitter sizes in the ratio of 1/J (J>1) and a differential ...
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JPH09219630A |
To realize a differential circuit in which complete linearity can be obtained even if a cross connection is performed for the circuit on a semiconductor integrated circuit. This circuit is composed of a means performing a logarithmic tra...
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JP2639350B2 |
PURPOSE: To realize an operational amplifier reducing a rising time/falling time. CONSTITUTION: When the gate voltage of P-channel FETs 16, 18 is decreased by an input signal voltage at signal input terminals 101, 102 in a differential a...
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JP2641408B2 |
A CMOS differential operational amplifier has a fully differential structure to improve the output swing and a cascode amplification structure to improve the operating speed. This amplifier includes: a differential input stage 21 which r...
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JP2637630B2 |
The present invention is directed to a method of and an apparatus for detecting an angular velocity and a rotation angle of a rotary member and for controlling a motor disposed to drive the rotary member. In the present invention, first ...
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JP2639028B2 |
PURPOSE:To prevent the generation of overlearning and to accelerate the learning of an unlearned pattern by providing the subject device with a teacher signal pattern comparing means, a changing value calculation storing means and a load...
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JP2638494B2 |
PURPOSE: To obtain a circuit converting an input voltage signal into complementary current signals of a noninverting phase and an inverting phase by giving the input voltage signal to transistors(TRs) being components of a current mirror...
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JPH09204485A |
To accelerate arithmetic speed without exerting any adverse influence upon accuracy by setting the gate width and gate length of MOS so that a time constant to be decided by a resistance value at the time of MOS conduction inside an MOS ...
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JPH09204414A |
To provide an inexpensive dielectric simulation device which can be practically used in terms of engineering and to provide a dielectric simulation method. A noninverted item calculation means 22 calculates the noninverted term Qp in acc...
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JPH09199951A |
To provide an output stage for an operational amplifier swingable close to a power supply voltage and having a low output impedance. The output stage for an operational amplifier energized by a 1st supply voltage conductor 102 and a 2nd ...
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JPH09198366A |
To provide a low voltage, super low power conductance mode neuron. A neural network 1 contains plural memory cells 15 and 17 having conductances which can individually execute programming and a neuron 5 connected to the memory cells 15 a...
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JPH09198458A |
To provide an anlog multiplier capable of correcting phase errors due to circuit delay. Two input signals S1 and S2 to be multiplied are respectively inputted through a single balance conversion circuit SBC to a multiplication core MT an...
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JP2634994B2 |
PURPOSE: To provide a fuzzy logic electronic controller depending on so called inferring operation in which the prescribed membership function of a logical variable is substantially constituted as a preposition being at least one front p...
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JP2635443B2 |
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