Title:
【発明の名称】LSSDインタフェース
Document Type and Number:
Japanese Patent JP2003523520
Kind Code:
A
Abstract:
An interface in an integrated circuit allows an LSSD storage element and a non-LSSD storage element to function together in the same scan chain. The interface has a data lock-up module, a test enable module, a master observe module, and a clock generator module. The data lock-up module latches data to be scanned into the integrated circuit through the scan chain. The test enable module indicates the status of a tester for testing the integrated circuit. The clock generator module generates a write clock and separate, non-overlapping master and slave scan clocks for a master latch and a slave latch in the LSSD storage element. The master observe module selectively asserts the slave scan clock prior to the master scan clock in order to latch the initial data bit appearing at the master latch.
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Inventors:
Sanhani Amit Day
Application Number:
JP2001560702A
Publication Date:
August 05, 2003
Filing Date:
February 14, 2001
Export Citation:
Assignee:
Sun Microsystems, Inc.
International Classes:
G01R31/28; G01R31/3185; H01L21/822; H01L27/04; (IPC1-7): G01R31/28; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Ryuka Akihiro