Title:
弱く順序付けられたストレージシステムにおいてメモリバリアコマンドを発行するための方法および装置
Document Type and Number:
Japanese Patent JP2012528399
Kind Code:
A
Abstract:
Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands.
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Inventors:
Thomas Philip Spire
James Norris Defenderfa
Thomas Andrew Sartorius
James Norris Defenderfa
Thomas Andrew Sartorius
Application Number:
JP2012513214A
Publication Date:
November 12, 2012
Filing Date:
May 26, 2010
Export Citation:
Assignee:
Qualcomm, Inc.
International Classes:
G06F12/08
Domestic Patent References:
| JP2008535064A | 2008-08-28 | |||
| JP2008535068A | 2008-08-28 | |||
| JPH05233422A | 1993-09-10 | |||
| JPS55147744A | 1980-11-17 |
Foreign References:
| US6275913B1 | 2001-08-14 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Kuroda Shinpei
Kuroda Shinpei
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