Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP3379970
Kind Code:
B2
Abstract:
PURPOSE:To obtain a semiconductor storage device wherein difference is not generated in timing margin of access time, write recovery, etc., for chip selection signal of two systems. CONSTITUTION:A CS buffer circuit is constituted as follows. A node A connecting a CS1 buffer to which a/CS1 signal is inputted and a CS2 buffer to which a C52 signal is inputted turns to an active level when the/CS1 signal is in the state of an active level, independently of the level change of the CS2 signal.
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Inventors:
Kiyotaka Akai
Application Number:
JP33432291A
Publication Date:
February 24, 2003
Filing Date:
November 20, 1991
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L27/11; G11C11/407; G11C11/41; H01L21/8244; (IPC1-7): G11C11/407; G11C11/41
Domestic Patent References:
| JP59160883A | ||||
| JP1118289A |
Attorney, Agent or Firm:
Kenichi Hayase