Title:
【発明の名称】半導体デバイスおよび製造方法
Document Type and Number:
Japanese Patent JP3400459
Kind Code:
B2
Abstract:
A semiconductor device whose packing density is high and which has a lot of functions. This device is manufactured by joining semiconductor elements to each other by solid phase welding through metallic thin films. Since the semiconductor elements, which have conventionally been joined to each other with an adhesive or solder, are joined by the method of the invention, the strength, heat radiating property, and dimensional accuracy of the joint are improved and the length of wiring is shortened or the wiring itself can be omitted. Semiconductor elements are stacked by using this joining method, and hence a high-density semiconductor device which performs arithmetic operation at a high speed and has a high reliability is manufactured.
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Inventors:
Yasuhiko Sasaki
Akiomi Kawano
Masaya Horino
Mitsuo Usami
Masahide Tokuda
Akiomi Kawano
Masaya Horino
Mitsuo Usami
Masahide Tokuda
Application Number:
JP51256397A
Publication Date:
April 28, 2003
Filing Date:
September 20, 1995
Export Citation:
Assignee:
Hitachi, Ltd.
International Classes:
H01L21/98; H01L25/065; H01L25/10; (IPC1-7): H01L25/065; H01L21/02; H01L25/07; H01L25/18
Domestic Patent References:
| JP456262A | ||||
| JP5109593A | ||||
| JP3171643A | ||||
| JP362566A | ||||
| JP4148525A |
Attorney, Agent or Firm:
Yasuo Sakuta