Title:
半導体素子の配線形成方法
Document Type and Number:
Japanese Patent JP4071029
Kind Code:
B2
Abstract:
A method for forming a wire in a semiconductor device, in forming a titanium film and a titanium nitride film as a barrier metal layer, which can deposit a titanium film and a titanium nitride film each in a different chamber by removing a titanium oxide film used as an insulating film made of upper titanium bonding with oxygen in air as the upper portion of a titanium film is exposed to air by a plasma process and then depositing a titanium nitride film, and as a result can reduce the throughput time of chamber equipment since the partial utilization of the system of the chamber equipment is enabled by driving another chamber even in case one of the chambers breaks down.
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JPH04299606 | HIGH FREQUENCY HIGH OUTPUT TRANSISTOR |
Inventors:
Yun-Acho
Application Number:
JP2002105153A
Publication Date:
April 02, 2008
Filing Date:
April 08, 2002
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H01L21/28; H01L21/768; H01L21/3205; H01L21/3213; H01L23/52
Domestic Patent References:
JP6097111A | ||||
JP9172083A |
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida
Jun Ishida