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Title:
複数の同期コードを有する並列データ通信
Document Type and Number:
Japanese Patent JP4228051
Kind Code:
B2
Abstract:
A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.

Inventors:
Eman Gregory E
Application Number:
JP2003501161A
Publication Date:
February 25, 2009
Filing Date:
May 28, 2002
Export Citation:
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Assignee:
NXP B.V.
International Classes:
H04L25/02; H04L7/00; H04L25/14; H04L25/49; H04L7/04
Domestic Patent References:
JP1188049A
JP8102729A
JP10247175A
JP6152636A
JP57162119A
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Takeshi Sekine
Takahashi