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Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP5194804
Kind Code:
B2
Abstract:

To provide a technology of detecting an abnormal state (output short circuit state and input-open state) of an external terminal without increasing costs in a semiconductor integrated circuit.

The semiconductor integrated circuit (MCU) includes a plurality of I/O circuits (IO1 to IO4), a monitor target designating circuit (DPSEL), and an abnormality detecting circuit (PCDET). The plurality of I/O circuits (IO1 to IO4) are provided corresponding to a plurality of external terminals (P1 to P4). The monitor target designating circuit (DPSEL) variably designates a monitor target external terminal from among the plurality of external terminals (P1 to P4). The abnormality detecting circuit (PCDET) detects the output short circuit state of the monitor target external terminal when the I/O circuit corresponding to the monitor target external terminal functions as an output circuit, and detects the input-open state of the monitor target external terminal when the I/O circuit corresponding to the monitor target external terminal functions as an input circuit.

COPYRIGHT: (C)2009,JPO&INPIT


Inventors:
Hideki Nakamura
Tachibana Dai
Application Number:
JP2008000991A
Publication Date:
May 08, 2013
Filing Date:
January 08, 2008
Export Citation:
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Assignee:
Fujitsu Semiconductor Limited
International Classes:
H03K17/08; G01R31/28
Domestic Patent References:
JP6350061A
JP8274614A
JP63273346A
JP1253315A
JP55160866A
JP2004311608A
Foreign References:
WO2006087844A1
Attorney, Agent or Firm:
Furuya Fumio
Toshihide Mori



 
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