Title:
半導体集積回路装置およびそれを用いた非接触/接触電子装置ならびに携帯情報端末
Document Type and Number:
Japanese Patent JP5215154
Kind Code:
B2
Abstract:
The semiconductor integrated circuit includes: a pair of antenna terminals; a rectifier; a source-voltage terminal; a shunt regulator; a series regulator. When the voltage of the inside source line rises to or above a first set voltage, the shunt regulator passes a pull-down current through a pull-down transistor. When the voltage of the inside source line drops to or below the second set voltage, the series regulator passes a pull-up current through a pull-up transistor. The first set voltage is set to be higher than the second set voltage in voltage level. With the semiconductor integrated circuit, the competition of actions of the two regulators is prevented. The semiconductor integrated circuit is arranged to work in contact and noncontact operation modes, and a stable source voltage can be supplied to an internal circuit thereof.
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Inventors:
Kazuki Watanabe
Naotaka Tsunoda
Naotaka Tsunoda
Application Number:
JP2008312938A
Publication Date:
June 19, 2013
Filing Date:
December 09, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G05F1/56; G05F1/00; G06K19/07
Domestic Patent References:
| JP2000348152A | ||||
| JP2008152690A | ||||
| JP2001504676A |
Foreign References:
| WO2006117834A1 | ||||
| WO2005072065A2 |
Attorney, Agent or Firm:
Shizuyo Tamamura