ＳＯＩウエハおよびその製造方法 - Mitsubishi Electric Corporation

Title:

ＳＯＩウエハおよびその製造方法

Document Type and Number:

Japanese Patent JP5933289

Kind Code:

B2

Abstract:

An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.

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Inventors:

Kazuhiro Shimizu
Junichi Yamashita
Sai Takuichiro

Application Number:

JP2012037024A

Publication Date:

June 08, 2016

Filing Date:

February 23, 2012

Export Citation:

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Assignee:

Mitsubishi Electric Corporation

International Classes:

H01L27/12; H01L21/02

Domestic Patent References:

JP6196379A
JP9153603A
JP8037137A
JP2004146461A
JP2002164521A
JP2007036279A
JP2008294408A
JP2011077506A
JP1120850A
JP2003078115A
JP2012129450A
JP2012089540A

Foreign References:

US20080265323

Attorney, Agent or Firm:

Yoshitake Hidetoshi
Takahiro Arita

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