Title:
電子回路用の基板およびその製造方法
Document Type and Number:
Japanese Patent JP6803369
Kind Code:
B2
Abstract:
A substrate (1, 10) for electrical circuits, comprising at least one metal layer (2,3, 14) and a paper ceramic layer (11), which is joined face to face with the at least one metal layer (2,3, 14) and has a top side and bottom side (11a, 11b), wherein the paper ceramic layer (11) has a large number of cavities in the form of pores. Especially advantageously, the at least one metal layer (2, 3, 14) is connected to the paper ceramic layer (11) by means of at least one glue layer (6, 6a, 6b), which is produced by applying at least one glue (6a′, 6a″, 6b′, 6b″) to the metal layer (2,3, 14) and/or to the paper ceramic layer (11), wherein the cavities in the form of pores in the paper ceramic layer (11) are filled at least at the surface by means of the applied glue (6a′, 6a″, 6b′,6b″).
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Inventors:
Mayer, Andreas
Schmid, Karlsten
Schmid, Karlsten
Application Number:
JP2018500918A
Publication Date:
December 23, 2020
Filing Date:
July 18, 2016
Export Citation:
Assignee:
Rogers Germany GmbH
International Classes:
H05K1/03; B32B5/18; B32B7/12; B32B9/00; B32B9/04; B32B15/04; B32B15/20; B32B27/00; C09J133/10; C09J163/00; C09J175/04; C09J179/04
Domestic Patent References:
| JP10017838A | ||||
| JP62268631A | ||||
| JP63274197A | ||||
| JP1242470A | ||||
| JP60056531U |
Attorney, Agent or Firm:
Mamoru Kuwagaki
▲吉▼川 俊雄
Kana Ichikawa
▲吉▼川 俊雄
Kana Ichikawa