Title:
4TH QUADRANT MULTIPLICATION CIRCUIT
Document Type and Number:
Japanese Patent JP3880730
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To permit driving by low voltage by making a 1st voltage compression circuit constructed with P channel MOSFET and making a 2nd voltage compression circuit constructed with an N channel MOSFET.
SOLUTION: A P channel voltage compression circuit 101 steps down input voltage Vin (a) and reference voltage Vref 1 in a prescribed ratio and outputs them. An N channel voltage compression circuit 102 steps down input voltage Vin (b) and the reference voltage Vref 1 in a prescribed ratio. It is possible to apply voltage that is higher than the voltage Vref 1 to the gate voltage of PMOSs 40 to 43 of a current conversion circuit 106 and to apply voltage that is lower than the voltage Vref 1 to the gate voltage of PMOSs 20 to 23 of 1st and 2nd voltage conversion circuits 103 and 104. Thus, it is possible to operate the PMOSs 20 to 23 in a pentode area even if power supply voltage Vcc is low.
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Inventors:
Takanobu Takeuchi
Application Number:
JP22973898A
Publication Date:
February 14, 2007
Filing Date:
August 14, 1998
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Domestic Patent References:
| JP8161413A | ||||
| JP11355075A |
Attorney, Agent or Firm:
Aoyama Aoi
Masahiro Ishino
Masahiro Ishino
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