Title:
マシンラーニング及びディープラーニングアプリケーション向けの適応マトリックス乗算加速器
Document Type and Number:
Japanese Patent JP7273746
Kind Code:
B2
Abstract:
An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit,a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.
Inventors:
Dongyang Jian
Dimin Niu
honzhong jang
Dimin Niu
honzhong jang
Application Number:
JP2020027401A
Publication Date:
May 15, 2023
Filing Date:
February 20, 2020
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G06F17/10; G06F7/50; G06F7/52; G06F17/16; G06N3/063
Foreign References:
| US20140032625 | ||||
| US20070233769 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki
Tadahiko Ito
Shinsuke Onuki