Title:
ANALOG ARITHMETIC CIRCUITRY
Document Type and Number:
Japanese Patent JP3532080
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an analog arithmetic circuit with small circuit scale and low power consumption.
SOLUTION: When a control signal ct 11 is at high level, switches 14 and 15 are connected and an input capacitor 11 and a feedback capacitor 12 are connected with an invertible amplifier 1. In this case, an input signal in 1 from an input terminal 10 is subjected to sample-and-hold by control of a sampling switch 13 and an output signal out 1 is outputted from an output terminal 16. In addition, when a control signal ct 12 is at high level, switches 24 and 25 are connected and an input capacitor 21 and a feedback capacitor 22 are connected with the invertible amplifier 1. In this case, an input signal in 2 from an input terminal 20 is subjected to sample-and-hold. Thus, the circuit scale is minimized and the power consumption is reduced by sharing a single invertible amplifier in plural analog arithmetic circuitry.
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Inventors:
Suzuki, Kunihiko
Shu, Nagaaki
Shu, Nagaaki
Application Number:
JP27329197A
Publication Date:
May 31, 2004
Filing Date:
September 22, 1997
Export Citation:
Assignee:
TAKATORI IKUEIKAI:KK
International Classes:
G06G7/186; G06G7/16; (IPC1-7): G06G7/16; G06G7/186
Attorney, Agent or Firm:
高橋 英生 （外１名）
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