Title:
ANALOG MULTIPLIER
Document Type and Number:
Japanese Patent JP3520175
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress cross modulation distortion due to unnecessary higher harmonic distortion and distortion of an input signal which are unnecessary for output by equipping an analog multiplier composed of a CMOS with an adding circuit which supplies an addition/subtraction signal needed for multiplying operation without any distortion.
SOLUTION: Respective unit circuits, i.e., a 1st adding circuit having a 1st MOS transistor(TR) composed of M4 and a 2nd MOS TR of M9, a 2nd adding circuit having a 1st MOS TR composed of M6 and a 2nd MOS TR of M10, a 3rd adding circuit having a 1st MOS TR composed of M7 and a 2nd MOS TR of M11, and a 4th adding circuit having a 1st MOS TR composed of M8 and a 2nd MOS TR of M12 are used to obtain a combination of two input signals and their inverted signals, i.e.. four addition/subtraction signals in total needed for analog multiplication without any distortion.
Inventors:
Yamamoto, Takeshi
Kasagi, Yoshitaka
Kasagi, Yoshitaka
Application Number:
JP8105597A
Publication Date:
April 19, 2004
Filing Date:
March 31, 1997
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06G7/163; H03G3/10; (IPC1-7): G06G7/163; H03G3/10
Attorney, Agent or Firm:
須山 佐一