To provide an arithmetic circuit which processes at a high speed and does not consume much electric power.

In an arithmetic circuit, a plurality of AND circuits 90, a plurality of half-adders HA, and a plurality of full-adders FA are arranged in an array-like state and a multi-bit adder 91 is arranged in the last stage. The adder 91 in the last stage is driven by means of a high-voltage source of 3 V and the other adders are driven by means of low-voltage sources of 2 V. In the preceding stage of the last-stage adder 91, level converting circuits 92 are arranged. The circuits 92 respectively convert the low-voltage levels of the signals inputted from the adders in the preceding stage into high-voltage levels. Since the last-stage adder 91 is operated with the high voltage, the operating speed of the arithmetic circuit can be increased. Since the other adders are operated with the low voltages, in addition, the power consumption of the circuit can be reduced. Moreover, since the level converting circuits 92 are arranged in the preceding stage of the last-stage adder 91, the number of the circuits 92 and, accordingly, the circuit scale of the arithmetic circuit can be reduced as compared with the case where the level converting circuits are arranged closer to the input side.