Title:
ARITHMETIC DEVICE AND PRODUCT-SUM ARITHMETIC SYSTEM
Document Type and Number:
Japanese Patent JP2021039477
Kind Code:
A
Abstract:
To improve accuracy of arithmetic operations in a circuit of an analog system that performs product-sum operations.SOLUTION: An arithmetic device includes a plurality of arithmetic circuit units, a signal output circuit, and a common wiring unit. The common wiring unit electrically connects a plurality of signal output lines of the signal output circuit and a plurality of input lines provided to each of the plurality of arithmetic circuit units. The plurality of arithmetic circuit units include a first arithmetic circuit unit and a second arithmetic circuit unit. Electric signals output from the plurality of signal output lines of the signal output circuit are input to the plurality of input lines provided to each of the first and second arithmetic circuit units, via the common wiring unit, as electric signals responsive to input values. An extension direction of the plurality of output lines of the first arithmetic circuit unit and an extension direction of the plurality of output lines of the second arithmetic circuit unit are configured to be parallel to each other.SELECTED DRAWING: Figure 19
Inventors:
FUJINAMI YASUSHI
Application Number:
JP2019159456A
Publication Date:
March 11, 2021
Filing Date:
September 02, 2019
Export Citation:
Assignee:
SONY CORP
International Classes:
G06G7/16; G06G7/14; G06N3/063
Attorney, Agent or Firm:
Junichi Omori
Mitsuru Takahashi
Teppei Nakamura
Ori Akira
Masayoshi Sekine
Ayako Kaneko
Shintaro Kanayama
Chiba Ayako
Shiraka Tomohisa
Mitsuru Takahashi
Teppei Nakamura
Ori Akira
Masayoshi Sekine
Ayako Kaneko
Shintaro Kanayama
Chiba Ayako
Shiraka Tomohisa