Title:
ARITHMETIC PROCESSING APPARATUS AND ARITHMETIC PROCESSING METHOD
Document Type and Number:
Japanese Patent JP2019168851
Kind Code:
A
Abstract:
To provide an arithmetic processing apparatus and an arithmetic processing method capable of being configured to reduce a circuit area and to speed up arithmetic processing.SOLUTION: The arithmetic processing apparatus according to an embodiment includes an arithmetic processing circuit 12, a conversion circuit 21, an integrator 22, and a comparator 23. The arithmetic processing circuit 12 includes a plurality of arithmetic processing elements 13 connected in series, and sequentially executes a plurality of arithmetic processes. The arithmetic processing element 13 receives first and second time signals, and generates and outputs third and fourth time signals obtained by delaying the first and second time signals by a time corresponding to a weighting factor and input data. The conversion circuit 21 converts a difference between the third and fourth time signals output from the arithmetic processing circuit 12 into an analog signal or a digital signal for each of the plurality of arithmetic processes. The integrator 22 integrates a plurality of analog signals or a plurality of digital signals converted by the conversion circuit 21. The comparator 23 compares the integration result obtained by the integrator 22 with a reference value.SELECTED DRAWING: Figure 4
Inventors:
TACHIBANA FUMIHIKO
Application Number:
JP2018055166A
Publication Date:
October 03, 2019
Filing Date:
March 22, 2018
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
G06N3/063; G06F7/523; G06G7/60; G06T1/40
Domestic Patent References:
| JP2017228295A | 2017-12-28 | |||
| JP2004110420A | 2004-04-08 | |||
| JPH1153335A | 1999-02-26 |
Attorney, Agent or Firm:
Kurata Masatoshi
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken