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Title:
BOUNDARY SCAN REGISTER
Document Type and Number:
Japanese Patent JPH11281710
Kind Code:
A
Abstract:

To improve the rate of failure detection and the rate of design failure detection and to improve test efficiency, by shortening a test pattern by performing the setting of logical state and observation associated with a test on as many nodes of a user circuit to be tested as possible, white suppressing reduction in the degree of integration due to increase in the number of test circuits.

By providing an input-side multiplexer with a multiplexer M3 as well as a multiplexer M1 to be a multiplexer of three inputs and alternative selection, it is possible to observe a user circuit by a TSDI. Furthermore, by providing a boundary scan register with a circuit for a signal TSDO to output a signal SDO to be outputted to a next another boundary scan register to a node in the user circuit, it is possible to set the logical state of the user circuit.


Inventors:
KONDO HISASHI
Application Number:
JP8358998A
Publication Date:
October 15, 1999
Filing Date:
March 30, 1998
Export Citation:
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Assignee:
KAWASAKI STEEL CO
International Classes:
G06F11/22; H01L21/822; H01L27/04; G01R31/28; (IPC1-7): G01R31/28; G06F11/22; H01L27/04; H01L21/822
Attorney, Agent or Firm:
Satoshi Takaya (2 outside)



 
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