PURPOSE: To make it possible to use a CCD memory at a high speed with low power consumption, by changing operating frequencies and driving voltages in stand-by mode and operation mode.

CONSTITUTION: In stand-by mode, a clock voltage driving CCD memory M is lowered and the memory is driven at the lowest-limit frequency (point D) where operation is possible by this voltage. In operation mode, the clock voltage is increased and it is driven at the highest-limit frequency (point A) where the operation is possible by this voltage. Namely, CCD memory driver circuit 1F converts basic clocks (fmax) and (fmin) from OFF circuit OR into clocks of freuqencies at points A and D and then supplies them to CCD memory M by way of driver D. Then, the clock voltage of memory M is shaped by a transistor, etc., and switch by a voltage switching circuit in accordance with chip selector signal CS. In this way, high speed operation in operation mode and low power consumption in stand-by mode realized.