Title:
CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2008187152
Kind Code:
A
Abstract:
To suppress warpage in a circuit device manufactured by a wafer level package technique.
A semiconductor substrate 20 used by the circuit device 10 has a circuit element 22, and an electrode 24 connected to the circuit element 22. A wiring layer 40 having a projection 41 connected to the electrode 24 is provided at the side of the main surface of the semiconductor substrate 20, and a metal layer 70 is provided at a side opposite to the main surface of the semiconductor substrate 20.
Inventors:
YAMAMOTO TETSUYA
OKAYAMA YOSHIHISA
YANASE YASUYUKI
SAWAI TETSUO
OKAYAMA YOSHIHISA
YANASE YASUYUKI
SAWAI TETSUO
Application Number:
JP2007021882A
Publication Date:
August 14, 2008
Filing Date:
January 31, 2007
Export Citation:
Assignee:
SANYO ELECTRIC CO
International Classes:
H01L23/12
Attorney, Agent or Firm:
Sakaki Morishita