CIRCUIT DEVICE FOR REDUCTION OF SWITCHING FAULT

Title:

CIRCUIT DEVICE FOR REDUCTION OF SWITCHING FAULT

Document Type and Number:

Japanese Patent JPH11163700

Kind Code:

A

Abstract:

To surely evade occurrence of faults even against a high level of feeding voltage by increasing the time delay of a switching signal as the feeding voltage level rises and supplying such switching signal to an output drive stage.

An output drive stage 11 consisting of an N-channel MOS transistor TR is connected to an input terminal 3 at its following position via the inverters 8 and 9. In the same way, an output drive stage 12 consisting of an N-channel MOS TR is connected to the terminal 3 at its following position via a delay element 13 and an inverter 10. The inverters 8, 9 and 10 and the element 13 are connected between both levels of feeding voltage VCC and reference voltage VSS. Under such conditions, the element 13 functions to increase the delay time as the voltage VCC rises. In other words, the higher the voltage VCC rises, the larger the switch-on/off time delay becomes for the means 11 and 12.

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Inventors:

MANYOKI ZOLTAN
SICHERT CHRISTIAN
SCHNEIDER RALF
BARTENSCHLAGER RAINER

Application Number:

JP27776398A

Publication Date:

June 18, 1999

Filing Date:

September 30, 1998

Export Citation:

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Assignee:

SIEMENS AG

International Classes:

H03K17/16; H03K19/003; H03K17/12; (IPC1-7): H03K17/16; H03K17/12

Attorney, Agent or Firm:

Toshio Yano (3 outside)

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