COMPUTING DEVICE AND PRODUCT-SUM COMPUTING SYSTEM

Japanese Patent JP2020160887

A

To provide a computing device, etc., with which it is possible to simplify a circuit configuration and realize a high-speed arithmetic processing.SOLUTION: The computing device comprises a plurality of input line pairs and one or more product-sum computing devices. A signal pair is inputted to the plurality of input line pairs within an input period. The product-sum computing device includes a plurality of multiplication units, a storage unit, a charge unit, and output unit. The plurality of multiplication units generate, on the basis of each signal of the signal pair, a positive load charge that corresponds to a positive load multiplication value with a positive load value and a negative load charge that corresponds to a negative load multiplication value with a negative load value. The storage unit stores the positive and negative load charges. The charge unit charges the storage unit with electricity after the input period. The output unit executes threshold determination on the voltage of the storage unit by a prescribed threshold after the start of a charge and outputs a positive product-sum signal that represents the sum of positive load multiplication values and a negative product-sum signal that represents the sum of negative load multiplication values. The charging of each product-sum computing device is executed in a common charge mode, with a common threshold set as the prescribed threshold.SELECTED DRAWING: Figure 4

YOSHIDA HIROSHI

JP2019060707A

October 01, 2020

March 27, 2019

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SONY CORP

G06G7/60; G06F17/10; G06G7/14; G06G7/16; G06G7/184; G06N3/063

Junichi Omori
Mitsuru Takahashi
Teppei Nakamura
Ori Akira
Masayoshi Sekine
Ayako Kaneko
Shintaro Kanayama
Chiba Ayako
Shiraka Tomohisa

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