To reduce a problem wherein bit variation varying for every continuously sent input data causes power consumption to increase due to switching increase in data writing to or reading from a storage device or the like, or causes interference between signal lines on a transmission line.
This data processor comprises a means for comparing the present n-bit output data with next n-bit output data and detecting whether inversion is performed every corresponding bit, a means for determining whether the number of detected bit inversions is more than n/2, a means for creating an additional bit indicating whether the present output data is inverted with respect to the next output data based on the determination result, and a means for inverting and outputting all bits of the next output data when the number of bit inversions is more than n/2 as the determination result and outputting the next output data as it is when the number of bit inversions is n/2 or less.
Fujitsuna Hideyoshi
Osamu Suzawa