To decrease the number of elements by making connections with memories of different access styles by sharing an access signal generation part.

The data processor 101 is equipped with a CPU part 107 which is put in charge of data processing, and interface parts 102 and 103 which are put in charge of the input and output of data to and from memories 109 and 110. Here, the interface parts 102 and 103 consists of control registers 104 and 105 which specify the access styles of the memories 109 and 110 and an access control part which generates an access signal for the memories 109 and 110. The control registers 104 and 105 and access control part are connected by a signal line for the access mode signal indicating the access styles of the memories 109 and 110. Then the access control part is so constituted that it is shared by the interface parts 102 and 103, and is equipped with a means which selectively controls the control registers 104 and 105.