PURPOSE: To provide an economical memory system to be applied to a large scale data capacity system.
CONSTITUTION: Respective modules are divided into cache memories 105, 107 and non-volatile storage devices 109, 111. Respective modules have their individual power supplies 101, 103, so that even when one of the power supplies 101, 103 is failed, the other module is not influenced by the failure. A specific block of data is not stored in the cache memory and storage device (e.g. 105, 109) of one module. Respective correction blocks of data are respectively stored in the cache memory (e.g. 105) of one module and the storage device (e.g. 111) of the other module. Thereby even when one power supply is failed, data are not lost. Since the devices 109, 111 are backed up by batteries 115, 117, data are not lost even when both the power supplies 101, 103 are failed.
| JP2001014283 | COMPUTER SYSTEM |
| JPH05265858 | MICROPROCESSOR |
| WO/2014/169025 | METHODS AND APPARATUS FOR IMPROVING PERFORMANCE OF SEMAPHORE MANAGEMENT SEQUENCES ACROSS A COHERENT BUS |
SHIYANKAA SHIN
FUORESUTO RII UEIDO
| JPH02118745A | 1990-05-07 |