DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK

Title:

DECODING SYSTEM AND PHYSICAL LAYOUT FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK

Document Type and Number:

Japanese Patent JP2023153778

Kind Code:

A

Abstract:

To provide an improved decoding system and physical layout for an analog neural memory system which uses a non-volatile memory cell.SOLUTION: An analog neural memory system includes a plurality of vector matrix multiplication arrays, a plurality of low voltage row decoders, and a plurality of global high voltage row decoders. Each of the low voltage row decoders provides a row decoder function for one of the plurality of vector matrix multiplication arrays, and each of the global high voltage row decoders is shared by two of the plurality of vector matrix multiplication arrays and provides a high voltage signal to two of the plurality of low voltage row decoders.SELECTED DRAWING: None

Inventors:

TRAN HIEU VAN
VU THUAN
STANLEY HONG
STEPHEN TRINH
LY ANH
TRAN HAN
NGUYEN KHA
PHAM HIEN

Application Number:

JP2023111962A

Publication Date:

October 18, 2023

Filing Date:

July 07, 2023

Export Citation:

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Assignee:

SILICON STORAGE TECH INC

International Classes:

G11C11/54; G06F12/00; G06F17/16; G06G7/16; G06G7/60; G06N3/065; G11C7/18; G11C16/04; G11C16/08

Attorney, Agent or Firm:

Patent Attorney Corporation Wisdom International Patent and Trademark Office

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