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Title:
DELAY CALCULATION METHOD, TIMING ANALYSIS METHOD, APPROXIMATION METHOD OF NETWORK OF CALCULATION OBJECT, AND DELAY CONTROL METHOD
Document Type and Number:
Japanese Patent JP2005038233
Kind Code:
A
Abstract:

To solve the problem in a delay calculation method that a precise delay value cannot be determined because it really performs the zero potential approximation of near wiring the potential of which is fluctuated.

The delay calculation method considering a near net of a delay calculation object net in a semiconductor integrated circuit comprises a near net internal resistance selection process S003 for selecting a combination of static states of a near net driving cell, a coupling capacity grounding process S004 for multiplying a coupling capacity by a coefficient determined from the internal resistance or the like of the near net driving cell selected from the above process, and grounding the resulting value as the coupling capacity of the net of the delay calculation object, and a delay value derivation process S006 for deriving a delay value from a circuit obtained by these processes.


Inventors:
AMAKAWA NAOKI
ICHINOMIYA TAKAHIRO
SATO KAZUHIRO
Application Number:
JP2003275246A
Publication Date:
February 10, 2005
Filing Date:
July 16, 2003
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F17/50; G06G7/00; H01L21/82; H01L27/04; H03K5/14; (IPC1-7): G06F17/50; H01L21/82; H03K5/14
Attorney, Agent or Firm:
Akio Miyai
Makoto Ito