Title:
【発明の名称】多層プリント回路板へチップを装着するための構成
Document Type and Number:
Japanese Patent JP2003502852
Kind Code:
A
Abstract:
The present invention relates to an arrangement concerned with multilayer printed circuit boards that enables cavities in said board to be utilized more effectively. A substrate (14) that includes a chip (16) which is connected to the microstrips (17) of the substrate (14) by means of bonding wires (18) is placed on a bonding shelf (13) with the chip (16) orientated towards the bottom of the cavity (6). The microstrips (17) on the substrate (14) therewith come into contact with the microstrips (12) on the bonding shelf (13). The earth plane (15) of the substrate (14) is connected to the upper earth plane (2) by means of bonding wires (19). The arrangement means that the cavity (16) is utilized effectively, at the same time as the substrate (14) protects the underlying chips (7, 16) against mechanical influences.
Inventors:
Haruyu, Thomas
Application Number:
JP2001504729A
Publication Date:
January 21, 2003
Filing Date:
June 13, 2000
Export Citation:
Assignee:
Telefon Acty Boraget Elm Ericson (Pubble)
International Classes:
H05K3/46; H01L23/12; H01L23/13; H01L23/538; H01L23/66; H01L25/065; H01L25/07; H01L25/18; H05K1/02; H05K1/18; (IPC1-7): H01L25/065; H01L23/12; H01L25/07; H01L25/18; H05K3/46
Domestic Patent References:
| JPH06112344A | 1994-04-22 | |||
| JPH10135406A | 1998-05-22 | |||
| JPH1187549A | 1999-03-30 | |||
| JPH04219966A | 1992-08-11 | |||
| JPS6010764A | 1985-01-19 | |||
| JPS5586354U | 1980-06-14 |
Attorney, Agent or Firm:
Akira Asamura (3 outside)