Title:
デジタルノイズ低減装置及び方法及び映像信号処理装置
Document Type and Number:
Japanese Patent JP4693546
Kind Code:
B2
Abstract:
According to one embodiment, a horizontal noise reduction circuit is supplied with an input video signal and the filter characteristic thereof is controlled by a noise reduction level setting value. A frame delay circuit delays the input video signal by a period of one frame. An inter-frame difference amount information counting circuit outputs a count value obtained by counting a preset logical value of a binary-coded output derived based on a difference between a frame delay video signal and the input video signal for one screen. A noise reduction level generator generates a noise reduction level setting value corresponding to the count value and supplies the same to the horizontal noise reduction circuit and vertical noise reduction circuit as a control signal.
Inventors:
Toshiyuki Namioka
Application Number:
JP2005239096A
Publication Date:
June 01, 2011
Filing Date:
August 19, 2005
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H04N5/21
Domestic Patent References:
| JP8130664A | ||||
| JP9163373A | ||||
| JP2002519949A | ||||
| JP6078180A | ||||
| JP2025174A | ||||
| JP11017954A | ||||
| JP11215403A | ||||
| JP7066995A | ||||
| JP6319152A | ||||
| JP2003153077A | ||||
| JP10093930A | ||||
| JP2005160071A |
Attorney, Agent or Firm:
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto