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Title:
FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS63151080
Kind Code:
A
Abstract:

PURPOSE: To prevent a trap of hot carriers affecting a drain at the position of a spacer oxide film in a field effect transistor having a low concentration drain region structure (LDD structure) by forming a thermal oxide film having less trap level on the low concentration drain.

CONSTITUTION: A polycrystalline silicon is grown on a gate oxide film 2 to form a gate electrode 1, and with them as masks for an ion implantation low concentration impurity phosphorus ions are implanted to form a low concentration diffused region 5. Further, the whole surface is oxidized to form a thermal oxide film 4 on a spacer. Then, a vapor growth oxide film 3 is formed on the film 4 to form a spacer oxide film. Then, it is so anisotropically etched as to completely etch the oxide film off the electrode 1 to form the spacer oxide film made of the films 3 and 4 on the sidewalls of the electrode 1 and the film 2. Thus, even if hot carriers are generated to be invaded underneath the spacer oxide film, the oxide film on the drain is formed of the thermal oxide having a less trap level and accordingly not trapped.


Inventors:
KURIYAMA HIROKO
Application Number:
JP29953686A
Publication Date:
June 23, 1988
Filing Date:
December 16, 1986
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L21/336; H01L29/78; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Toshio Nakao



 
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