PURPOSE: To make it possible to make operation check by the operation of only one CPU in a multi-CPU system suing an FIFO by providing newly a bus interface section and a spurious control signal generating section.
CONSTITUTION: By outputting data to be transferred to a CPU to DBUS 1 and generating a WR signal to FIFO 3, data on the DBUS 1 are stored in FIFO 3. The data bus of the CPU 2 and controlling signal are separated from FIFO in a bus interface section 5 and made to high impedance state. A spurious READ signal TR is generated in FIFO from a spurious control signal generating section 6 provided in the CPU 1, and data stored in FIFO are outputted to a DBUS 3. A spurious WRITE signal TW is generated from the spurious control signal generating section to FIFO 4, and data on the DBUS 3 are stored in FIFO 4. An RL signal is generated to FIFO 4 and the operation check of FIFO is completed by comparing read data by the CPU 1 with the data outputted first from the CPU 1 to FIFO 3.
MIYAZAKI JUN
NISHIDA HIDEJI
